We are using LS1046A with SerDes and I was wondering if the clock for SerDes line can be provided after the POR when the device has accessed to its I2C bus?
The datasheet is not very clear about the clock sequencing. Is the Serdes clocks has to be provided before POR?
We have an I2C controlled Clock Generator, therefore it can't be programmed before the LS1046A has I2C working.
SerDes reference clocks must be applied before PORESET_B is deasserted.
If this requirement is violated the RSTRQSR1[SRDS_RST_RR] is set which prevents normal operation of the processor.
It is possible to use CPLD to control the clock generator.
Thank you! Very clear now.
Is it the same for RGMII clock : EC1_GTX_CLK125?
> Is it the same for RGMII clock : EC1_GTX_CLK125?
RGMII does not use SerDes.