SYS_PLL_RAT and PLLPGSR

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SYS_PLL_RAT and PLLPGSR

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jasonhendrix
Contributor V

My question is: why is PLLPGSR:CFG = 4 (an invalid value) when SYS_PLL_RAT = 3?

Hi, I'm trying to verify that my clocking is OK after a JTAG reset.  I'm having trouble with UARTs, which are driven by the platform clock, so I'm checking the platform clock configuration. 

My RCW in QSPI flash, and in the DCFG_CCSR_RCWSR1 register is 0x0608000A.  I think this is a pretty standard value for the LS1021ATWR dev board that I'm using.  Parsing this value yields a SYS_PLL_RAT of 3, for a multiplier of 3.  Now going to the PLLPGSR register in section 4.3.5 of the LS1021ARM, it says that the CFG field is based on SYS_PLL_RAT.  My system has a '4' in this CFG field.  The doc also says that valid values are 7 through 16, which is hard to reconcile with the SYS_PLL_RAT values of 2, 3, or 4.  It seems likely that I'm not understanding what these fields mean, or that there is a typo in the PLLPGSR:CFG description. Even so, why a 4 and not a 3?

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jasonhendrix
Contributor V

Here's what worked for me.  In configurations->target settings->Hardware or Simulator Connection -> target, select LS1021A_TWR.  Click Edit.

Select Execute target reset.  Select Initialize target.  Select memory Configuration.

Now, when I launch, I need to click "suspend" in the Debug pane.  PC is in DDR where I expect it, RCW and other registers are not reset values, this is also good.

Then I can click reset.  PC goes to 0x0, but other registers, esp RCW retain their values.  Can now proceed with u-boot debugging as described in online documentation.

One more thing - after the above configuration, the debugger would connect, but the reset would always fail.  Clicking on details elaborated with "Reset failed".  Closing and restarting CW fixed this problem. 

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jasonhendrix
Contributor V

More info on the clocking issue on this thread: UART Reset debugging.

Basically, when running from power-up, everything works fine.  When connecting with the debugger, I get an apparent reset (not expected), and the platform clock runs at 200MHz instead of 300 MHz.

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ufedor
NXP TechSupport
NXP TechSupport

> I get an apparent reset (not expected), and the platform clock runs at 200MHz instead of 300 MHz.

How exactly the debugger connection is established?

Please check that RCW is not overrided.

1) You wrote:

> LS1021ATWR dev board that I'm using

Please provide U-Boot log for NOR booting.

2) Which onboard switches settings you're using for the QSPI boot?

3) Please provide binary image of the RCW in SPI Flash.

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jasonhendrix
Contributor V

Here is the RCW binary file I loaded into flash.  You can also see it in the QSPI boot log reply.

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jasonhendrix
Contributor V

Debugging with CodeWarrior TAP over USB.  Definitely overriding RCW, otherwise I can't debug u-boot because the RCW status registers and the scratch register used to hold the start address are mostly 0x0.  Attached is my jtag ini file. 

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ufedor
NXP TechSupport
NXP TechSupport

> Definitely overriding RCW

This is not needed if a valid RCW is present in the RCW source (NOR or QSPI).

> Here is the RCW binary

Sorry, where?

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jasonhendrix
Contributor V

Here's what worked for me.  In configurations->target settings->Hardware or Simulator Connection -> target, select LS1021A_TWR.  Click Edit.

Select Execute target reset.  Select Initialize target.  Select memory Configuration.

Now, when I launch, I need to click "suspend" in the Debug pane.  PC is in DDR where I expect it, RCW and other registers are not reset values, this is also good.

Then I can click reset.  PC goes to 0x0, but other registers, esp RCW retain their values.  Can now proceed with u-boot debugging as described in online documentation.

One more thing - after the above configuration, the debugger would connect, but the reset would always fail.  Clicking on details elaborated with "Reset failed".  Closing and restarting CW fixed this problem. 

View solution in original post

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jasonhendrix
Contributor V

"... not necessary..."  I agree that it shouldn't be necessary.  But, like I said, it's difficult to debug u-boot from qspi with the reset values.  At what point during the u-boot debug process are the RCW values and start address loaded?

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jasonhendrix
Contributor V

Is there a way to export my launch/debug configuration and analyze it for reset options?

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jasonhendrix
Contributor V

For fun, here is the QSPI boot log:

SW2[1:8] 0001 0101

SW3[1:8] 0110 1101

U-Boot 2015.01+SDKv1.9+gd614817 (Apr 14 2016 - 15:50:30)

CPU:   Freescale LayerScape LS1021E, Version: 2.0, (0x87081120)

Clock Configuration:

       CPU0(ARMV7):1000 MHz,

       Bus:300  MHz, DDR:800  MHz (1600 MT/s data rate),

Reset Configuration Word (RCW):

       00000000: 0608000a 00000000 00000000 00000000

       00000010: 30000000 00007900 40025a00 21046000

       00000020: 00000000 00000000 00000000 20000000

       00000030: 20024800 881b7540 00000000 00000000

Board: LS1021ADEG

I2C:   ready

DRAM:  1 GiB

Using SERDES1 Protocol: 48 (0x30)

MMC:   FSL_SDHC: 0

SF: Detected N25Q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB

*** Warning - bad CRC, using default environment

EEPROM: NXID v1

PCIe1: Root Complex no link, regs @ 0x3400000

PCIe2: disabled

In:    serial

Out:   serial

Err:   serial

SEC0: RNG instantiated

SATA link 0 timeout.

AHCI 0001.0300 1 slots 1 ports ? Gbps 0x1 impl SATA mode

flags: 64bit ncq pm clo only pmp fbss pio slum part ccc

scanning bus for devices...

Found 0 device(s).

SCSI:  Net:   eTSEC1 is in sgmii mode.

eTSEC2 is in sgmii mode.

eTSEC1 [PRIME], eTSEC2, eTSEC3

=>

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jasonhendrix
Contributor V

Here is the NOR booting setup:

SW2[1:8] 1000 1111

SW3[1:8] 0110 0101

U-Boot 2015.01+ls1+g3281947 (Jul 30 2015 - 20:01:52)

CPU:   Freescale LayerScape LS1021E, Version: 2.0, (0x87081120)

Clock Configuration:

       CPU0(ARMV7):1000 MHz,

       Bus:300  MHz, DDR:800  MHz (1600 MT/s data rate),

Reset Configuration Word (RCW):

       00000000: 0608000a 00000000 00000000 00000000

       00000010: 70000000 00007900 e0025a00 21046000

       00000020: 00000000 00000000 00000000 20000000

       00000030: 00080000 881b7340 00000000 00000000

Board: LS1021ATWR

CPLD:  V2.0

PCBA:  V1.0

VBank: 0

I2C:   ready

DRAM:  1 GiB

Using SERDES1 Protocol: 112 (0x70)

Firmware 'Microcode version 0.0.1 for LS1021a r1.0' for 1021 V1.0

QE: uploading microcode 'Microcode for LS1021a r1.0' version 0.0.1

Flash: 128 MiB

MMC:   FSL_SDHC: 0

EEPROM: NXID v1

PCIe1: Root Complex no link, regs @ 0x3400000

PCIe2: Root Complex no link, regs @ 0x3500000

In:    serial

Out:   serial

Err:   serial

SEC0: RNG instantiated

SATA link 0 timeout.

AHCI 0001.0300 1 slots 1 ports ? Gbps 0x1 impl SATA mode

flags: 64bit ncq pm clo only pmp fbss pio slum part ccc

scanning bus for devices...

Found 0 device(s).

SCSI:  Net:   eTSEC2 is in sgmii mode.

eTSEC1, eTSEC2, eTSEC3 [PRIME]

Hit any key to stop autoboot:  0

=>

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