Hi, Dear NXP Tech Support Team:
Hello Kevin He,
Please refer to the following bit 416-418 in LS1021 RCW configuration, please refer to 010 and 100 options.
416-418 EC1 Selects the functionality
assigned to the EC1 pins:
EC1_TXD3, EC1_TXD2,
EC1_TXD1, EC1_TXD0,
EC1_TX_EN, EC1_GTX_CLK,
EC1_GTX_CLK125,
EC1_RXD3, EC1_RXD2,
EC1_RXD1, EC1_RXD0,
EC1_RX_CLK, EC1_RX_DV
Options:
000 RGMII1
001 GPIO3[2:14]
010 CAN2_TX, CAN1_TX, Reserved, Reserved,
Reserved, Reserved, Reserved, CAN2_RX,
CAN1_RX, Reserved, Reserved, Reserved, Reserved
011 MII1 (Note: EC3 must be 011 for MII support.)
100 SAI1_TX_DATA, SAI2_TX_DATA,
SAI1_TX_SYNC, SAI2_TX_SYNC, SAI1_TX_BCLK,
SAI2_TX_BCLK, EXT_AUDIO_MCLK2,
SAI1_RX_DATA, SAI2_RX_DATA, SAI1_RX_SYNC,
SAI2_RX_SYNC, SAI1_RX_BCLK, SAI2_RX_BCLK
101 FTM1_CH5, FTM1_CH7, FTM1_CH3,
FTM1_CH2, FTM1_FAULT, FTM1_EXTCLK,
Reserved, FTM1_CH4, FTM1_CH6, FTM1_CH1,
FTM1_CH0, FTM1_QD_PHA, FTM1_QD_PHB
110 Reserved
111 Reserved
Please refer to RCW provided in the pre_built image ISO.
rcw/ls1021atwr/RSR_PPS_70$ xxd rcw_1000.bin
00000000: aa55 aa55 01ee 0100 0608 000a 0000 0000 .U.U............
00000010: 0000 0000 0000 0000 7000 0000 0000 7900 ........p.....y.
00000020: e002 5a00 2104 6000 0000 0000 0000 0000 ..Z.!.`.........
00000030: 0000 0000 2000 0000 0008 0000 881b 7340 .... .........s@
00000040: 0000 0000 0000 0000 0957 0200 ffff ffff .........W......
00000050: 09ee 0200 6010 0000 09ea 085c 0050 2880 ....`......\.P(.
00000060: 0861 0040 83c1 eb81 .a.@....
ls1021atwr/rcw/ls1021atwr/SSR_PNS_30$ xxd rcw_1000.bin
00000000: aa55 aa55 01ee 0100 0608 000a 0000 0000 .U.U............
00000010: 0000 0000 0000 0000 3000 0000 0000 7900 ........0.....y.
00000020: e002 5a00 2104 6000 0000 0000 0000 0000 ..Z.!.`.........
00000030: 0000 0000 1800 0000 0008 0000 481b 7340 ............H.s@
00000040: 0000 0000 0000 0000 0957 0200 ffff ffff .........W......
00000050: 09ee 0200 6010 0000 09ea 085c 0050 2880 ....`......\.P(.
00000060: 0861 0040 e7a2 5a83 .a.@..Z.
In fact, I consider your DDR problem should be caused by the improper DDR controller configuration in u-boot.
If you are bringing up a new target board, you need to customize DDR controller configuration section in u-boot according to your target board.
We often suggest customers create a QCVS project according to DDR datasheet or reading from SPD, then use DDRv tool to do optimization and validation.
Have a great day,
TIC
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What are the first 8 bytes of the RCW? aa55 aa55 01ee 0100? After power up, when I read the RCW register inside the processor with a JTAG/COP, I do not see these bytes. The RCW contains next 56 bytes. But I can see with a logic analyzer that these 8 bytes are coming out the sd-card. And the CPU doesn't boot.
Where should I look? Any ideas?
Thank you.
Best regards,
Sanjay
Got it, thanks a lot Yiping
Regards
Kevin
On Tue, Sep 18, 2018 at 3:19 AM, Yiping Wang <admin@community.nxp.com>