QorlQ T2080 Eval Board IFC and CPLD

[KLN]

Hi,

What is the purpose of connecting IFC to CPLD in QorlQ T2080 Evaluation board?

[yipingwang]

• CPLD
— PCBA version identify
— Manages system power and reset sequencing
— Configures DUT, board, clock with dynamic
— Reset and interrupt monitor and control
— General fault monitoring and logging

The IFC GPCM interface is used to access the registers of CPLD and FPGA.

[KLN]

I'm still unclear on what kind of use case especially IFC interface between CPLD and NXP T2080.

[yipingwang]

There are many reasons:

1) Many POR config pins (cfg_*_*) are multiplexed with IFC pins. FPGA ensures these pins are in desired state during POR

2) Single NOR flash has been divided in two banks. Implies user can have boot code in Bank 0 and Bank 4. This is done by FPGA by inverting the MSB of address line

3) If user wants to boot from NAND or NOR, FPGA can re-route CS0 accordingly

4) Converntionally, registers implemented in FPGA could be accessed through FPGA

5) Some of the modes of IFC which cannot be tested using existing flashes, can be implemented on FPGA during validation phase...