QorIQ T1040 DDR3L interface

[vaishakvasanth]

Hi,

I am working on interfacing DDR3L SDRAM with T1040 processor. I need to prepare a flowchart or an algorithm to read/write into memory. I have the details of the processor(requirements) and the commands of the SDRAM to read and write.
I would like it if someone told me the procedure to interface and read/write.

Thank you

[ufedor · Accepted solution]

1) DDR SDRAM controller interface signals connection requirements and recommendations are provided in the AN3940 - Hardware and Layout Design Considerations for DDR3 SDRAM:

https://www.nxp.com/webapp/Download?colCode=AN3940&location=null

2) DDR controller registers settings and initialization are described in the AN4039_PowerQUICC and QorIQ DDR3 settings:

https://www.nxp.com/docs/en/application-note/AN4039.pdf

3) Considering that interface signals for DDR3 and DDR4 SDRAM are nearly identical it is possible to refer to the following NXP reference designs:

1. a) Discrete DDR4 SDRAM – T1023RDB design files:

https://www.nxp.com/downloads/en/printed-circuit-boards/T1023RDB-PC-DS.zip

1. b) DDR3 UDIMM – T1040RDB design files:

https://www.nxp.com/downloads/en/schematics/T1040RDB_DESIGNFILES.zip

4) Please find attached CodeWarrior initialization scripts:

T1023RDB_init_core.tcl

T1040RDB_init_core.tcl

The scripts contain DDR controller initialization sections which contains all necessary registers settings.

After the DDR controller initialization the processor's core can read and write memory data by executing load and store assembler instructions – please refer to the E5500 Reference Manual, 3.4.3.2 Load and Store Instructions:

https://www.nxp.com/webapp/Download?colCode=E5500RM