Please help me to understand the impact of errata A-004737. What is UART break interrupt?Does this break interrupt leads to a UART serial interrupt?

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Please help me to understand the impact of errata A-004737. What is UART break interrupt?Does this break interrupt leads to a UART serial interrupt?

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Contributor II

A-004737: BREAK detection triggered multiple times for a single break assertion
Description: A UART break signal is defined as a logic zero being present on the UART data pin for a time
longer than (START bit + Data bits + Parity bit + Stop bits). The break signal persists until the
data signal rises to a logic one.
A received break is detected by reading the ULSR and checking for BI = 1. This read to ULSR
clears the BI bit. After the break is detected, the normal handling of the break condition is to
read the URBR to clear the ULSR[DR] bit. The expected behavior is that the ULSR[BI] and
ULSR[DR] bits do not get set again for the duration of the break signal assertion. However, the
ULSR[BI] and ULSR[DR] bits continue to get set each character period after they are cleared.
This continues for the entire duration of the break signal.
At the end of the break signal, a random character may be falsely detected and received in the
URBR, with the ULSR[DR] being set.
Impact: The ULSR[BI] and ULSR[DR] bits get set multiple times, approximately once every character
period, for a single break signal. A random character may be mistakenly received at the end of
the break.
Workaround: The break is first detected when ULSR is read and ULSR[BI]=1. To prevent the problem from
occurring, perform the following sequence when a break is detected:
1. Read URBR, which returns a value of zero, and clears the ULSR[DR] bit
2. Delay at least 1 character period
3. Read URBR again, which return a value of zero, and clears the ULSR[DR] bit
ULSR[BI] remains asserted for the duration of the break. The UART block does not trigger any
additional interrupts for the duration of the break.
This workaround requires that the break signal be at least 2 character-lengths in duration.
This workaround applies to both polling and interrupt-driven implementations.
Fix plan: No plans to fix

Errata attached for the reference.

Thanks.

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NXP TechSupport
NXP TechSupport

T2080 Reference Manual, Table 18-4 states that in case of break interrupt, interrupt request is cleared by reading line status register ULSR. So - yes, after BI is cleared by reading ULSR register, if next BI will be set after this first BI clearing, it will generate interrupt once again.


Have a great day,
Alexander
TIC

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