Phy-less 1Gbps ethernet at LS2088A

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Phy-less 1Gbps ethernet at LS2088A

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iaevsikov
Contributor I

Hi.

I am using Ethernet at LS2088A connected directly to FPGA. Without PHY.
And i have some issues.

MAC-layer works on 10Mbps while PCS-layer works on 1Gbps.

Linux on LS2088 detects link from FPGA and vice versa. But packets can't go through the channel. At FPGA's side i can see idles at 1Gbps, but every byte of packet "longs" 100 tics(according to 10mbps). Also when i'm trying to enable loopback at LS2088A's serdes - i'm getting packets. But it accepts packets at 10Mbps speed.
Ethtool says that interface works on 1Gbps:

Settings for eth2:
        Supported ports: [ ]
        Supported link modes:   Not reported
        Supported pause frame use: No
        Supports auto-negotiation: No
        Supported FEC modes: Not reported
        Advertised link modes:  Not reported
        Advertised pause frame use: No
        Advertised auto-negotiation: No
        Advertised FEC modes: Not reported
        Speed: 1000Mb/s
        Duplex: Full
        Port: Twisted Pair
        PHYAD: 0
        Transceiver: internal
        Auto-negotiation: on
        MDI-X: Unknown
        Link detected: yes

I can't change "port" setting. I was trying different versions of Linux kernel. The latest one is 4.19.26.

According to MAC driver it's ussing 1000-FD mode by default:

struct fixed_phy_status status = {
.link = 1,
/* fixed-phys don't support 10Gbps speed for now */
.speed = 1000,
.duplex = 1,

};

Could you tell me how to set up channel properly. Tried many OS settings and SerDes registers. Thanks

1 Solution
513 Views
bpe
NXP TechSupport
NXP TechSupport


What actually happens when you specify the PHY to be a fixed-phy,
is that the driver doesn't look for an external PHY and skips it's
initialization. It does not alter the behaviour of the on-chip
PCS which by default still expects certain type of autonegotiation
to occur over the link. fixed-phy only makes the system assume
that everything beneath the MAC occurs properly with power-on defaults.  This may
work if your FPGA mimics SGMII PHY-side autonegotiation.  For
whatever else, before any suggestion can be given, it is important to
know what kind of autonegotiation your FPGA supports, if at all.


Have a great day,
Platon

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2 Replies
514 Views
bpe
NXP TechSupport
NXP TechSupport


What actually happens when you specify the PHY to be a fixed-phy,
is that the driver doesn't look for an external PHY and skips it's
initialization. It does not alter the behaviour of the on-chip
PCS which by default still expects certain type of autonegotiation
to occur over the link. fixed-phy only makes the system assume
that everything beneath the MAC occurs properly with power-on defaults.  This may
work if your FPGA mimics SGMII PHY-side autonegotiation.  For
whatever else, before any suggestion can be given, it is important to
know what kind of autonegotiation your FPGA supports, if at all.


Have a great day,
Platon

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

View solution in original post

513 Views
iaevsikov
Contributor I

Thank you for explanation, Platon.
SGMII PHY-side autonegotiation helped.

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