P4080 WatchDog Timer - Interrupt

[jameshorton]

I'm doing some BSP work trying to get an interrupt to fire using hte Time Base Registers (upper/lower), Timer Control Register, Machine Status Register and either the HID0 or CTBENU/CTBSELU registers.

I see the TB is actively incrementing so it must be getting clocked.    I've written 0x0002_9000 to the MSR and tried two values (0x2804_0000, 0x3804_0000) in the TCR.   I never see the TSR change.  What else am I missing?  I haven't attached an interrupt handler yet but from what I'm seeing, I don't think it would be called yet.

[scottwood · Accepted solution]

You've selected bit 8 of the timebase for the watchdog to trigger.  With a timebase of 100 MHz (it's usually slower than that), you'd see bit 8 of the timebase flip after around 11.4 years.  Remember that the bits are numbered starting from the most significant bit.

[jameshorton]

That was the problem, I was counting the bits from the LSB. Thanks!