P2041: confusion related to "CONFIG_SYS_TEXT_BASE"

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P2041: confusion related to "CONFIG_SYS_TEXT_BASE"

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gouravjain
Contributor IV

Hi,

In my board, based on P2041rdb, i'm trying to understand u-boot bring-up sequence.

U-boot is flashed in NOR flash(size: 128MB), connected over eLBC-->CS0 interface.

in P2041RDB.h file, we have

CONFIG_SYS_FLASH_BASE     0xE800_0000 [ Assume we have to assign starting address of NOR flash, where first file will be residing. Here RCW we are keeping].

In another flag,

CONFIG_SYS_TEXT_BASE       0xEFF8_0000 [This is the NOR flash address where U-Boot is stored].

But i got confused what address we must assign in "CONFIG_SYS_TEXT_BASE" NOR flash address or RAM address, where u-boot should relocate while booting??

---

Gourav Jain

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11 Replies

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yipingwang
NXP TechSupport
NXP TechSupport

Hello gourav jain,


Please refer to the following definition in include/configs/P2041RDB.h in u-boot provided in SDK, CONFIG_SYS_FLASH_BASE is the start address of NOR flash, CONFIG_SYS_TEXT_BASE is the start address of u-boot image on NOR flash. For NOR flash boot, instructions are fetched from NOR flash to be executed directly, so CONFIG_SYS_TEXT_BASE is defined as the address on NOR flash.

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE    0xeff40000
#endif

#define CONFIG_SYS_FLASH_BASE           0xe0000000

Please refer to NOR flash memory map.

pastedImage_1.png

pastedImage_2.png

Thanks,

Yiping

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gouravjain
Contributor IV

Hi Yiping,

Let's assume RCW [0xE8000000] and u-boot [0xEFF40000] are fused in NOR flash. After POR, sequence will be following,

1) As per jumper settings, values will be sampled at cfg_rcw_src[0:4]. In our case we are setting NOR flash mode.

2) H_reset will be released and PBL will load RCW from NOR flash [0xE8000000] and store into RCW registers.

3) If there is no error from PBL. Then u-boot will be fetched from NOR flash address 0xEFF40000 and stored into DDR.

4) Then u-boot initialize DDR from reading SPD parameters.

Pls correct me if i'm wrong. Not sure how PBL will come to know u-boot is at 0xEFF40000 ....

--

Gourav 

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gouravjain
Contributor IV

Hi Yiping,

Kindly reply on above statements...

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yipingwang
NXP TechSupport
NXP TechSupport

Hello gourav jain,

 

For NOR u-boot, the instruction stored at the the address of reset vector will be fetched and executed firstly, u-boot will be executed form NOR flash directly to configure and initialize the target board, after u-boot initialize DDR controller, u-boot will copy code from NOR flash to DDR memory and jump to DDR to continue to run.

On PowerPC platform, processors will fetch instructions from 4K boot page at 0xFFFFF000 automatically after power on reset, this 4K boot page is defined in the default TLB entry and mapped to NOR flash physically when booting from NOR flash.

 

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
#endif

 

Thanks,

Yiping

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gouravjain
Contributor IV

hi Yiping,

Thanks for your reply...

You mentioned ,

 "4K boot page is defined in the default TLB entry and mapped to NOR flash physically when booting from NOR flash"

I wanted to find out where it mapped in tlb.c and found below set of codes. But couldn't found NOR address mapping. Can you pls help me where it is defined exactly??

/* TLB 1 */
/* *I*** - Covers boot page */
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff00000, it covered the 0xfffff000.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
* space is at 0xfff00000, it covered the 0xfffff000.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#else
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
#endif

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gouravjain
Contributor IV

How processor will come to know u-boot is at 0xEFF4_000 or some where else in NOR ??

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yipingwang
NXP TechSupport
NXP TechSupport

When each core comes out of reset, its MMU has one 4 KB page defined at 0x0_FFFF_Fnnn. Each core begins execution with the instruction at effective address 0x0_FFFF_FFFC.  The reset vector in u-boot deployed at (the end of) NOR flash is just mapped to this effective address.

Thanks,

Yiping

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vinothkumars
Senior Contributor III

Please Give, 

CONFIG_SYS_TEXT_BASE -> 0xE0000000

Thanks & Regards,

VinothS.

Regards,
Vinothkumar Sekar
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gouravjain
Contributor IV

Thanks Vinod.Why you are saying 0xE0000000.

Anyways, My system is booting properly with CONFIG_SYS_TEXT_BASE       0xEFF8_0000.

I just wanted to know what does that flag means?? NOR flash address or RAM address. I went through several threads and those made me bit confused about that.

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vinothkumars
Senior Contributor III

You want to assign NOR flash address for CONFIG_SYS_TEXT_BASE .  And please assign as per the attached link documents.

Please check (Table 59. NOR Flash Memory Map) from https://www.nxp.com/docs/en/supporting-information/QORIQ-SDK-2.0-IC-REV0.pdf .

From this address for u-boot as per document,

CONFIG_SYS_TEXT_BASE       0xEFF4_0000

Please check (4.4.10.6 System Memory Map) from https://www.nxp.com/docs/en/supporting-information/QORIQ-SDK-2.0-IC-REV0.pdf .

/*
* IFC Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xe0000000
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)

after mapping, we got 0xfe0000000 as per document.

Thanks,

VinothS.

Regards,
Vinothkumar Sekar
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gouravjain
Contributor IV

Hi Vinod,

U misunderstood my question little bit. 

As per you we should assign NOR flash memory location where u-boot is stored. Correct me if i'm wrong.

Then my next questions are,

1) where this flag is being used / what u-boot will do with this information? 

2) After Power On Reset, at what DDR location my u-boot will reside?

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