P1020RDB and Watchdog

[tomvogel]

I have a Freescale P1020rdb-pc development kit, Codewarrior Tap  and am using CodeWarrior 10.3 in Linux for development. (LinuxMint OS).

U boot source and toolchain is the from the Freescale SDK1.4 Yocto package.

U boot is working fine and I am currently building a suite of hardware tests starting from POST.

I was attempting to build a function to test the Watchdog and I have a couple of questions:

1) Can anyone point me to the correct reference manual that documents the watchdog timer registers. Reference is made to the TCR[WRC] register in the P1020 Reference Manual, but no details are given.

2) I looks as if uboot does not implement the internal watchdog in the p1020 correctly. I defined "CONFIG_WATCHDOG" but did not seem to work. Anyone had any experience here?

3) I noticed that the P1020RDB-PC has an external watchdog chip implemented.  I am assuming that this is optional should we wish to add a more reliable (external) watchdog to our own design.

thanks,

tom.

[yipingwang]

Section 5.3 of the P1020RM:

TCR[WRC] is defined more specifically for the implementation of the core in the integrated device. Watchdog timer reset control. This value is written into TSR[WRS] when a watchdog event occurs. WRC may be set by software but cannot be cleared by software, except by a software-induced reset. Once written to a non-zero value, WRC may no longer be altered by software.

00 No watchdog timer reset can occur

01 Force processor checkstop on second timeout of watchdog timer

10 Assert processor reset output (core_hreset_req) on second timeout of watchdog timer

11 Reserved

For WD details in the app.note "Watchdog Timer for e500"

http://cache.freescale.com/files/32bit/doc/app_note/AN2804.pdf