P1011 POR configuration pull-ups query

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P1011 POR configuration pull-ups query

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andyjones
Contributor II

I'm trying to build up a picture of what POR pins require external pull-ups/downs, as opposed to making use of internal pull-ups, on the P1011, but I'm struggling to get a consistent interpretation of data in two documents:

Document 1: Regarding Section 1.2, "Table 1. P1011 Pinout Listing" of

"P1011 QorIQ Integrated Processor Hardware Specifications, Document Number: P1011EC, Rev. 1, 03/2012", each Signal with a reference to Note 4 has the benefit of an internal Pull-Up applied during POR.  This does not apply to all signals associated with the POR configuration. Of the signals that do have this facility, some are normally I/O, others are normally Outputs.

Document 2: Regarding chapter 3, "Table 3-2. Reset configuration signals" of

"P1020 QorIQ Integrated Processor Reference Manual Supports: P1020 and P1011, Document Number: P1020RM, Rev. 6, 01/2013."

The table is introduced with the statement

"Most of the reset configuration signals have internal pull-up resistors so that if the signals are not driven, the default value is high (a one), as shown in the table. Some signals do not have pull-up resistors and must be driven high or low during the reset period."

and lists the functional signal names that are associated with reset configuration names, and the Default, which is expressed as:

"Must be driven": for all cfg_xxx_pllx inputs (some of which are normally Outputs or I/O without internal pull-ups, but others are I/O which Document 1 identifies as having Internal pull-ups, e.g. TSEC_1588_CLK_OUT, cfg_ddr_pll0 - and for which the group being 111 is a valid configuration), so how does the statement in italics above relate? Must it really be driven, or is it pulled up?

"All ones": for cfg_gpinput[0:15].  These do all have pull-ups, so this is consistent with Document 1.

"1" or strings of "1": Again, a problem as there are a number of examples that Document 1 suggests do not benefit from having pull-ups during POR,, e.g. I/O signal MSRCID0, cfg_elbc_ecc, or Output signal UART_SOUT0, cfg_eng_use[3].  Are these really all equipped with pull-ups or must they be driven?

Please tell me, what aspect have I overlooked?  Is the P1011 and P1020 data meant to be the same in respect of these POR configurations and pull-ups?

Thanks,

Andy Jones

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andyjones
Contributor II

Adding to the inconsistent/incomplete picture:

  1. Document 2, table 3-2 indicates where config pins must be driven, but table 3-3 suggests many do benefit from weak Pull ups during POR, so which is right?
  2. Document 2, table 3-3 appears to be an incomplete list: I would expect TSEC3_TXD[3:0] to be listed, and CFG_IO_PORTS3 also.  Why are they omitted, and is it relevant, as table 3-2 indicates they have got weak p-ups?
  3. Document 1 identifies CFG_DRAM_TYPE as an input, but Document 2 identifies this as an Output in table 3-1, and as I/O in figure 3-2

Is there a record of outstanding issues for either document that I should refer to?

Thanks,

Andy

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andyjones
Contributor II

A friendly response from NPX explained that Document 2 Table 3-2 is the correct source for POR configurations:

Yes, unfortunately our documents contain inaccuracies due to complexity of the devices. Let me briefly clarify situation with cfg signals. Table 3-2 of the manual is correct, use it as a reference which signals have internal pull-ups. In total 12 configuration signals do not have internal pull-ups, all these ones are related to PLL configurations. I hope this solves your issue, please let me know if not.

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ufedor
NXP Employee
NXP Employee

It is recommended to explicitly pull up or down each configuration signal in case it will be needed to alternate the signal's POR level in the future.

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andyjones
Contributor II

In the design in review at the moment, some of the POR config selections are relying on those temporary internal pull-ups, and are essentially not tracked away from the BGA, so if that is a Freescale QorIQ product recommendation that we should consider, can you guide me to that recommendation?

And in the mean time, the documentation still paints a confusing picture, which I'd like to have clarified.

Thanks,

Andy

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ufedor
NXP Employee
NXP Employee

It is possible to refer to the P1020RDB-PD design.

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