Number of PCIe ports in T2080

[abhijitpethkar]

Sir,

I would like to confirm the number of PCIe ports available on the T2080 processor. 

Our requirement is two numbers of PCIe host port, x4 Gen 3.0.

T2080 Product Brief states " Four PCI Express controllers (two support PCIe 2.0 and two support PCIe 3.0)". It does not state how many of them will act as host and how many will act as end point.

[r8070z]

Have a great day,

The T2080 has 4 PCIe controllers which all can be set as host (RC) simultaneously. 2 PCIe controllers can be configured as PCIe host port x4 @ 8 GT/s at the same time; one on the Serdes1 and the second on the Serdes2. You can check that in the T2080 reference manual available on the NXP site. See Table 19-1. SerDes Lanes Assignments and Multiplexing and HOST_AGT_PEX description in the  Table 4-14.

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[dale_blankenshi]

Serguei, you state that "2 PCIe controllers can be configured as PCIe host port x4 @ 8 GT/s at the same time; one on the Serdes1 and the second on the Serdes2", but the Reference Manual states in section 19.1.1.1.2, fourth bullet point, that "Only one PCIe in the device can support 8/5/2.5 GT/s. SRDS1 (PCIe4) and SRDS2 (PCIe1) may support these frequencies. Any combination in which both PCIe controllers support 8/5/2.5 GT/s is not allowed."

These two statements seem to contradict. My application currently only requires 5 GT/s on all lanes (two x4 ports and one x1 port), but I'd like the option of going to 8 GT/s on both x4 ports if possible. However, Table 19-1 appears to allow setting two x4 ports to 8GT/s and one x4 port to 5 GT/s (setting SRDS_PRTCL_S1 to 66 or 67, and setting SRDS_PRTCL_S2 to 1F). I don't need SATA, and my Ethernet needs are only 10/100/1000 Base-T, so I can use an external PHY on the RGMII pins.

Can anyone confirm that this would work?

[r8070z]

I am sorry but it is true, any combination in which both PCIe controllers support 8/5/2.5 GT/s is not allowed.