NXP LS1012a FRDM - Startup / Switch EL3 to EL2

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NXP LS1012a FRDM - Startup / Switch EL3 to EL2

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Contributor I

Hi everyone

For my Bachelor Thesis I try to port an OpenSource kernel (i.e. Muen SK) to the ARMv8-A AArch64 architecture and decided to use the NXP LS1012a FRDM evaluation board as the target platform. The Kernel is written in Ada/SPARK and therefore I use a JLink Edu Debugger with OpenOCD and GPS as the IDE.

Everything went well so far - after resetting the board and letting the U-Boot bootloader do its job I can load my code into RAM and run it in EL3. I am now trying to get from EL3 to EL2 in hypervisor mode but after a few instructions I get a lot of "Illegal Instructions" in the debugger as well as the executing code even though my binary doesn't contain such illegal or undefined instructions (see pictures in the appendix).

A similar variant of the startup code and the linker script was already tested on different hardware and in the simulator and worked. After three days of testing and reading, I think that I am missing something about the MMU in connection with the DDR initialization. You can find the current startup file and linker script in the appendix.

Does anyone have any idea or guess where I could find my mistake? I would appreciate your advices!

Thanks, David

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NXP TechSupport
NXP TechSupport

Thank you for your information.


Have a great day,
Pavel Chubakov

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Contributor I

Finally, I can confirm my assumptions. I wrote a static page table (i.e. I actually wrote a small Java application that generated the page tables) according to the ARM Cortex-A ARMv8 Programmer's Guide and the QorIQ LS1012A Reference Manual. With this changes, everything works perfectly!

Thanks again, David

PS: I hope that the NXP forum administrators didn't have too much work with my now somewhat unnecessary question. Sorry for that!

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Contributor I

After reading through the documentation again and a few tests, I think I can give myself a hint :smileyhappy:

I think that the U-Boot bootloader only sets the MMU ID map for  EL3. I therefore assume that I will have to create the ID mapping for EL2 myself and that I have to do this already in the initialization code on EL3 (because I place my code directly into RAM).

This solution would explain quite everything - because the instruction cache is enabled at EL3, a few instructions of my code running at EL2 are correctly translated and loaded into the cache. But all later instructions will be loaded from somewhere else in the memory and are therefore garbage. This would also explain why my code always threw an exception in a different place.

Of course I will update this post as soon as I have tested my findings.

David

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