Multibank DDR3 Interface!

[qammarabbas]

Hi,

I am interfacing 2 banks of DDR3L devices with T1042 processor. At this stage, i have got some schematics for reference but all of them either use a single bank or they use registered DIMMS. Can anybody please provide a schematic having multiple banks? I want to see how are the different groups (Address, Command, Control) terminated.

Thank you!

[ufedor · Accepted solution]

Connection schematics for the second bank is just the same as for the first one, just MCS1, MCKE1 and MODT1 should be used in place of MCS0, MCKE0 and MODT0.

Note that because of fly-by topology SDRAM chips of the second bank have to be placed under the chips of first bank on the opposite board surface (as on DIMM module).

General reference is AN3940 - Hardware and Layout Design Considerations for DDR3 SDRAM.

[qammarabbas]

Thank you. I want to know about how to terminate the address, clock and command group. Can you please elaborate that?

[ufedor]

In case of two banks all these signals should be terminated the same way as in case of single bank.