LS2088ARDB Target Initialization File for Micron DIMMs shipped with Rev F

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LS2088ARDB Target Initialization File for Micron DIMMs shipped with Rev F

284 Views
Contributor I

I am trying to bring up a bare-metal application on LS2088ARDB, ported from LS1043ARDB where it works.  I cannot get memory to initialize, even to do connection diagnostics, using the LS2088A-RDB connection profile and target initialization file provided with CodeWarrior and a CodeWarrior TAP.  We have several LS2088A-RDB boards.  It looks like the register settings in the target connection profile do not match the dual-rank 16GB Micron DIMMs that shipped with our LS2088A-RDB boards.

Is there an updated Target Initialization File that you can ship me for the updated DIMMs?

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12 Replies

230 Views
Contributor I

Let's start over. 

SUCCESSFUL ON LS1043A-RDB:
===========================

I have more than one LS1043A-RDB.  I am able to debug bare-metal code on any of them using CodeWarrior and a CodeWarrior TAP connected via USB. I am using a modified copy of the LS1043A_RDB connection profile and Target Initialization File provided with CodeWarrior.  The changes in the Target Initialization File were obtained by booting U-Boot / Yocto / Linux on the LS1043A_RDB and copying the CCSR memory controller register values into the Target Initialization File.

NOT SUCCESSFUL ON LS2088A-RDB:
===============================

I am attempting to start bare-metal debug on LS2088A-RDB boards.  I have attached two of them to CodeWarrior using the connection profile and target initialization file provided with CodeWarrior and a CodeWarrior TAP connected by USB.  When I run Connection Diagnostics, all tests pass until I get to "Test DDR memory access".  This includes "Test OCRAM memory access" which also passes.  "Test DDR memory access" fails with "cannot read from address 0x80000000".  This is the same procedure that we used successfully with LS1043A-RDB boards. 

We have ported the python DDR memory initialization routine into C and included it in our bare-metal application.  When I run the bare-metal C code, the code does not exit normally from the C version of this loop:

count = 0
while True:
      time.sleep(0.2)
      DDR_F04 = CCSR_LE_D(0x0000000001080f04 + id * 0x10000)
      count = count + 1
      if (DDR_F04 == 2):
         break
      if (count > 10):
         break

I don't know what this loop does because CCSR register 0x01080F04 is undocumented.

The D_INIT loop that follows the controller enable loop also fails to complete normally and D_INIT never turns off.

I have copied the CCSR register settings extracted from a U-BOOT initialization (above post dated 17 September) into the Target Initialization File.  These new settings do not appear to correct any of the symptoms.

 

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NXP TechSupport
NXP TechSupport

The DDR_F04[1] is "Memory controller idle" bit.

"1" corresponds to Memory controller idle state.

Please try to change the "count" to 20 and check the script behaviour.

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224 Views
Contributor I

No change in connection diagnostics behavior. 

Is there a way to debug a Target Initialization python script?

I had already tried MUCH longer timeouts in our C code without success.

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186 Views
NXP TechSupport
NXP TechSupport

Please provide textual dump of the DDR controller registers (range 0x01080000 - 0x0109FFFF) and current version of the CodeWarrior board configuration script for inspection.

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180 Views
Contributor I

This is CCSR register space for memory controller #1, extracted while Yocto was running:

# B::Data.Dump_(0x1080000..0x01080FFF)_/LONG_/DIALOG_/COLumns_8
# ________________address|________0________4________8________C________0________4________8________C_0123456789ABCDEF0123456789ABCDEF

# MD:01080000|>000007FF 00000000 000007FF 00000000 00000000 00000000 00000000 00000000 ................................
# MD:01080020| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:01080040| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:01080060| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:01080080| A8050422 80000422 00000000 00000000 00000000 00000000 00000000 00000000 "..."...........................
# MD:010800A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:010800C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:010800E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:01080100| 01131100 91660018 DED8F045 00512154 E5004000 00401141 03010421 00080200 ......f.E...T!Q..@..A.@.!.......
# MD:01080120| 1600046B 1C70071C DEADBEEF 00000000 03000000 00000000 00000000 00000000 k.....p.........................
# MD:01080140| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:01080160| 00220002 04401400 00000000 25500000 8A090705 C675060A 00000000 00000000 .."...@.......P%......u.........
# MD:01080180| 00000000 00000000 00000000 00000000 0B0C0E11 1214140F 00000000 00000000 ................................
# MD:010801A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:010801C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:010801E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:01080200| 00010421 00080200 00010421 00080200 00010421 00080200 00000000 00000000 !.......!.......!...............
# MD:01080220| 00000500 04400000 00000400 04400000 00000400 04400000 00000400 04400000 ......@.......@.......@.......@.
# MD:01080240| 00000000 00000000 00000000 00000000 03335900 00000000 00000000 00000000 .................Y3.............
# MD:01080260| 00000000 00000000 00000000 00000000 0000FFFF 00000000 00000000 00000000 ................................
# MD:01080280| DDEEEEED EEEDEEED 22111112 11121112 11EE0001 00000000 00000000 00000000 ..........."....................
# MD:010802A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:010802C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:010802E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................

"""
Copyright 2015-2016 Freescale Semiconductor, Inc.
Copyright 2016-2018 NXP.
All Rights Reserved

 This software is owned or controlled by NXP and may only be used strictly in accordance with the
 applicable license terms.  By expressly accepting such terms or by downloading, installing,
 activating and/or otherwise using the software, you are agreeing that you have read, and that you
 agree to comply with and are bound by, such license terms.  If you do not agree to be bound by the
 applicable license terms, then you may not retain, install, activate or otherwise use the software.
"""
import gdb
import time

from cw.dbg import ta
from cw.dbg import flash

from cw.dbg.rcw import SPRcwValidation

from initialization import *

# In order to connect to a board with a broken RCW, set the following variable to True
# Override RCW using a safe hard-coded RCW option
USE_SAFE_RCW = True

CORE_CONTEXT = ":ccs:LS2088A:CortexA72#0"
SAP_CORE_CONTEXT = ":ccs:LS2088A:SAP#0"

CPLD_ADDR = 0x20000000

# Because the QSPI controller cannot work at the same time with the
# IFC controller, this variable will enable QSPI boot and initialize
# only the QSPI and disable the IFC; you must also make some changes
# on the board - for this please see the section QSPI_BOOT from readme
# file.
QSPI_BOOT = 0

# Base address for DCFG and Reset registers;
# they will be used to test if RCW and PBI phases were successful or not
DCFG_BASE_ADDRESS = 0x1E00000
RESET_BASE_ADDRESS = 0x1E60000

DCSR_BASE_ADDRESS = 0x700000000

# Target access object
TA = ta.create()

###################################################################
# Prepare environment/convenience variables
###################################################################
def Prepare_Env():
    set_init_params(context=CORE_CONTEXT, dcsr_addr=DCSR_BASE_ADDRESS, fpga_addr=0x500000000 + CPLD_ADDR)
    gdb.execute("set $ddr_addr = 0x80000000")
    gdb.execute("set $ocram_addr = 0x18000000")

###################################################################
# Reset
###################################################################

def Reset():

    if USE_SAFE_RCW:
        # Set rcw_src to hard-coded RCW option
        TA.rcw.set_source(0x9F)

        if QSPI_BOOT == 0:
            # Make sure IFC_GRP_A_BASE Pin Configuration are set to 0b00, otherwise
            # programming NOR flash will not work.
            TA.rcw.set_data({15: 0x00000000})

        # add here if you need to override other particular RCW values

        TA.rcw.apply()

    else:
        # Perform a regular reset
        try:
            user_reset = int(gdb.parse_and_eval("$reset"))
            user_reset_delay = int(gdb.parse_and_eval("$reset_delay"))
        except gdb.error:
            user_reset = 1
            user_reset_delay = 0

        if user_reset:
            try:
                gdb.execute("cw_reset %d" % user_reset_delay)
            except gdb.error as exc:
                # check if RCW or PBI phases were successful
                # note: target accesses must be executed through SAP core
                TA.set_context(SAP_CORE_CONTEXT)
                SPRcwValidation(TA, DCFG_BASE_ADDRESS, RESET_BASE_ADDRESS).check_for_rcw_or_pbi_error()
                # if check_for_rcw_or_pbi_error does not detect the error, forward the initial exception
                raise exc

    Init_BRR()

    return

###################################################################
# Boot Release
###################################################################
def Init_BRR():

    # TODO: when we can detect the current context,
    # release all cores for SMP, current core for AMP

    # First set the secondary cores to debug mode after release
    DCSR_LE_M(0x7002C, 0x000000FE)
    # Write to BRR to release cores
    CCSR_LE_M(0x01e60060, 0x00000000ff)

    # Make sure the gdb threads are refreshed just after the BRR initialization
    TA.rc.refresh_threads()

    # Make sure the cores are stopped
    TA.rc.halt()

###################################################################
# TrustZone Initialization
###################################################################
def Init_TZASC():
    # TZASC
    for id in range(2):
        # Gate Keeper
        CCSR_LE_M(0x01100008 + id * 0x10000, 0x00000001)
        # Region Top Low 1
        CCSR_LE_M(0x01100128 + id * 0x10000, 0xffffffff)
        # Region Top High 1
        CCSR_LE_M(0x0110012C + id * 0x10000, 0xffffffff)
        # Region_Atributes_1
        CCSR_LE_M(0x01100130 + id * 0x10000, 0xc0000001)
        # Region_Id_Access_1
        CCSR_LE_M(0x01100134 + id * 0x10000, 0xffffffff)

###################################################################
# DDR Initialization
###################################################################
def DDRC_Wait_for_Idle(id):
    count = 0
    while True:
        time.sleep(0.2)
        controller_idle = CCSR_LE_D(0x0000000001080f04 + id * 0x10000) & 0x00000002
        count = count + 1
        if (controller_idle != 0):
            break
        if (count > 10):
            break

def DDRC_Wait_for_Reset(id):
    count = 0
    while True:
        time.sleep(0.2)
        in_reset = CCSR_LE_D(0x0000000001080260 + id * 0x10000) & 0x80000000
        count = count + 1
        if (in_reset != 0):
            break
        if (count > 10):
            break

def Reset_DDRC(id):
    DDR_CFG = CCSR_LE_D(0x0000000001080110 + id * 0x10000)
    CCSR_LE_M(0x0000000001080110 + id * 0x1000, DDR_CFG & 0x7FFFFFFF)

    DDRC_Wait_for_Idle(id)

    DDR_CFG_3 = CCSR_LE_D(0x0000000001080260 + id * 0x10000)
    CCSR_LE_M(0x0000000001080260 + id * 0x1000, DDR_CFG_3 | 0x80000000)

    DDRC_Wait_for_Reset(id)

def Init_DDRC(DDR_CLK):
    DDR1600_TH = 1350
    DDR1866_TH = 1666
    DDR2133_TH = 1900

# B::Data.Dump_(0x1080000..0x01080FFF)_/LONG_/DIALOG_/COLumns_8
# ________________address|________0________4________8________C________0________4________8________C_0123456789ABCDEF0123456789ABCDEF
#             MD:01080000|>000007FF 00000000 000007FF 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080020| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080040| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080060| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080080| A8050422 80000422 00000000 00000000 00000000 00000000 00000000 00000000 "..."...........................
#             MD:010800A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010800C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010800E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080100| 01131100 91660018 DED8F045 00512154 E5004000 00401141 03010421 00080200 ......f.E...T!Q..@..A.@.!.......
#             MD:01080120| 1600046B 1C70071C DEADBEEF 00000000 03000000 00000000 00000000 00000000 k.....p.........................
#             MD:01080140| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080160| 00220002 04401400 00000000 25500000 8A090705 C675060A 00000000 00000000 .."...@.......P%......u.........
#             MD:01080180| 00000000 00000000 00000000 00000000 0B0C0E11 1214140F 00000000 00000000 ................................
#             MD:010801A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010801C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010801E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080200| 00010421 00080200 00010421 00080200 00010421 00080200 00000000 00000000 !.......!.......!...............
#             MD:01080220| 00000500 04400000 00000400 04400000 00000400 04400000 00000400 04400000 ......@.......@.......@.......@.
#             MD:01080240| 00000000 00000000 00000000 00000000 03335900 00000000 00000000 00000000 .................Y3.............
#             MD:01080260| 00000000 00000000 00000000 00000000 0000FFFF 00000000 00000000 00000000 ................................
#             MD:01080280| DDEEEEED EEEDEEED 22111112 11121112 11EE0001 00000000 00000000 00000000 ..........."....................
#             MD:010802A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010802C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010802E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080300| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080320| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080340| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080360| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080380| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010803A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010803C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010803E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080400| 32C57554 D4BB0BD4 2EC2F554 D95D4001 00000000 00000000 00000000 00000000 Tu.2....T....@].................
#             MD:01080420| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080440| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080460| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080480| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010804A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010804C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010804E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080500| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080520| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080540| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080560| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080580| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010805A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010805C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010805E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080600| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080620| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080640| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080660| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080680| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010806A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010806C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010806E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080700| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080720| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080740| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080760| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080780| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010807A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010807C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010807E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080800| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080820| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080840| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080860| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080880| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010808A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010808C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010808E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080900| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080920| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080940| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080960| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080980| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010809A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010809C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:010809E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080A00| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080A20| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080A40| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080A60| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080A80| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080AA0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080AC0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080AE0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080B00| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080B20| 00008080 80000000 80080000 000000C0 00000000 00000000 00000000 00000000 ................................
#             MD:01080B40| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080B60| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080B80| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080BA0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080BC0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080BE0| 00000000 00000000 00000000 00000000 00000000 00000000 00020502 00000100 ................................
#             MD:01080C00| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080C20| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080C40| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080C60| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080C80| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080CA0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080CC0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080CE0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080D00| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080D20| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080D40| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080D60| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080D80| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080DA0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080DC0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080DE0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080E00| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080E20| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080E40| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080E60| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080E80| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080EA0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080EC0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080EE0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
#             MD:01080F00| 00000000 00000002 0000000C 14000C20 00000000 00000000 00000000 00000000 ............ ...................
#             MD:01080F20| 00000000 3C003F00 42004300 4A004D00 4E005100 46007000 00000000 00000000 .....?.<.C.B.M.J.Q.N.p.F........
#             MD:01080F40| 00000000 00000000 00000001 D4000000 14001600 18001A00 20002100 26002700 .........................!. .'.&
#             MD:01080F60| 1C000000 00009000 00000020 00000000 0070006E 00000000 00000000 00000000 ........ .......n.p.............
#             MD:01080F80| 00000000 00000000 00000000 00000000 00000000 80000000 00000000 31023002 .............................0.1
#             MD:01080FA0| 30023002 31023002 2F023002 30020000 00000003 1F1F1D20 1D1C1E1E 1E1E1B1F .0.0.0.1.0./...0.... ...........
#             MD:01080FC0| 1B1D1E1C 1E1E1C1F 1B1D1D1C 1F1D1D20 1C1D1E1D 1E1E1C1F 1B1D1D1C 1E1D1C1F ............ ...................
#             MD:01080FE0| 1C1D1D1D 1E1D1B1E 1B1D1C1B 1F1E1D1F 1C1D1D1D 1E1D1C1F 1C1D1C1B 1F000000 ................................

    for id in range(2):
    
        CCSR_LE_M(0x000000070012c800 + id * 0x1000, 0x63b30002)

        Reset_DDRC(id)

#       CCSR_LE_M(0x0000000001080130 + id * 0x10000, 0x02000000)
#       CCSR_LE_M(0x0000000001080000 + id * 0x10000, 0x000003ff)
#       CCSR_LE_M(0x0000000001080080 + id * 0x10000, 0xa8050322)
#       CCSR_LE_M(0x00000000010800c0 + id * 0x10000, 0x00000000)
#       CCSR_LE_M(0x0000000001080008 + id * 0x10000, 0x000003ff)
#       CCSR_LE_M(0x0000000001080084 + id * 0x10000, 0x80000322)
#       CCSR_LE_M(0x00000000010800c4 + id * 0x10000, 0x00000000)
#       CCSR_LE_M(0x0000000001080010 + id * 0x10000, 0x00000000)
#       CCSR_LE_M(0x0000000001080088 + id * 0x10000, 0x00000000)
#       CCSR_LE_M(0x00000000010800c8 + id * 0x10000, 0x00000000)
#       CCSR_LE_M(0x0000000001080018 + id * 0x10000, 0x00000000)
#       CCSR_LE_M(0x000000000108008c + id * 0x10000, 0x00000000)
#       CCSR_LE_M(0x00000000010800cc + id * 0x10000, 0x00000000)

        CCSR_LE_M(0x0000000001080130 + id * 0x10000, 0x03000000)
        CCSR_LE_M(0x0000000001080000 + id * 0x10000, 0x000007ff)
        CCSR_LE_M(0x0000000001080080 + id * 0x10000, 0xa8050422)
        CCSR_LE_M(0x00000000010800c0 + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x0000000001080008 + id * 0x10000, 0x000007ff)
        CCSR_LE_M(0x0000000001080084 + id * 0x10000, 0x80000422)
        CCSR_LE_M(0x00000000010800c4 + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x0000000001080010 + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x0000000001080088 + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x00000000010800c8 + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x0000000001080018 + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x000000000108008c + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x00000000010800cc + id * 0x10000, 0x00000000)

        if (DDR_CLK < DDR1600_TH):
            # 1333
            CCSR_LE_M(0x0000000001080100 + id * 0x10000, 0x010a1000)
            CCSR_LE_M(0x0000000001080104 + id * 0x10000, 0x90440018)
            CCSR_LE_M(0x0000000001080108 + id * 0x10000, 0x96906c44)
            CCSR_LE_M(0x000000000108010c + id * 0x10000, 0x0048e10e)
            CCSR_LE_M(0x0000000001080160 + id * 0x10000, 0x00220002)
            CCSR_LE_M(0x0000000001080164 + id * 0x10000, 0x01401400)
            CCSR_LE_M(0x0000000001080168 + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x000000000108016c + id * 0x10000, 0x02200000)
            CCSR_LE_M(0x0000000001080250 + id * 0x10000, 0x02247800)

            CCSR_LE_M(0x0000000001080118 + id * 0x10000, 0x03010001)
            CCSR_LE_M(0x000000000108011c + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x0000000001080200 + id * 0x10000, 0x00010001)
            CCSR_LE_M(0x0000000001080204 + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x0000000001080208 + id * 0x10000, 0x00010001)
            CCSR_LE_M(0x000000000108020c + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x0000000001080210 + id * 0x10000, 0x00010001)
            CCSR_LE_M(0x0000000001080214 + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x0000000001080220 + id * 0x10000, 0x00000500)
            CCSR_LE_M(0x0000000001080224 + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x0000000001080228 + id * 0x10000, 0x00000400)
            CCSR_LE_M(0x000000000108022c + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x0000000001080230 + id * 0x10000, 0x00000400)
            CCSR_LE_M(0x0000000001080234 + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x0000000001080238 + id * 0x10000, 0x00000400)
            CCSR_LE_M(0x000000000108023c + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x0000000001080124 + id * 0x10000, 0x14500100)
            CCSR_LE_M(0x0000000001080174 + id * 0x10000, 0x8675f606)
            CCSR_LE_M(0x0000000001080190 + id * 0x10000, 0x0708090b)
            CCSR_LE_M(0x0000000001080194 + id * 0x10000, 0x0c0d0e09)

            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x862000c0)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x862000f0)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x86200070)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x962000c0)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x962000f0)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x96200070)

        elif (DDR_CLK < DDR1866_TH):
            # 1600
            CCSR_LE_M(0x0000000001080100 + id * 0x10000, 0x010c1000)
            CCSR_LE_M(0x0000000001080104 + id * 0x10000, 0x90550018)
            CCSR_LE_M(0x0000000001080108 + id * 0x10000, 0xbbb48e44)
            CCSR_LE_M(0x000000000108010c + id * 0x10000, 0x00490111)
            CCSR_LE_M(0x0000000001080160 + id * 0x10000, 0x00220002)
            CCSR_LE_M(0x0000000001080164 + id * 0x10000, 0x03401400)
            CCSR_LE_M(0x0000000001080168 + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x000000000108016c + id * 0x10000, 0x13300000)
            CCSR_LE_M(0x0000000001080250 + id * 0x10000, 0x02335800)

            CCSR_LE_M(0x0000000001080118 + id * 0x10000, 0x03010211)
            CCSR_LE_M(0x000000000108011c + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x0000000001080200 + id * 0x10000, 0x00010211)
            CCSR_LE_M(0x0000000001080204 + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x0000000001080208 + id * 0x10000, 0x00010211)
            CCSR_LE_M(0x000000000108020c + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x0000000001080210 + id * 0x10000, 0x00010211)
            CCSR_LE_M(0x0000000001080214 + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x0000000001080220 + id * 0x10000, 0x00000500)
            CCSR_LE_M(0x0000000001080224 + id * 0x10000, 0x04000000)
            CCSR_LE_M(0x0000000001080228 + id * 0x10000, 0x00000400)
            CCSR_LE_M(0x000000000108022c + id * 0x10000, 0x04000000)
            CCSR_LE_M(0x0000000001080230 + id * 0x10000, 0x00000400)
            CCSR_LE_M(0x0000000001080234 + id * 0x10000, 0x04000000)
            CCSR_LE_M(0x0000000001080238 + id * 0x10000, 0x00000400)
            CCSR_LE_M(0x000000000108023c + id * 0x10000, 0x04000000)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x0000000001080124 + id * 0x10000, 0x18600100)
            CCSR_LE_M(0x0000000001080174 + id * 0x10000, 0x8675f607)
            CCSR_LE_M(0x0000000001080190 + id * 0x10000, 0x08090a0c)
            CCSR_LE_M(0x0000000001080194 + id * 0x10000, 0x0d0f100b)

            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x862004c0)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x862004f0)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x86200470)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x962004c0)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x962004f0)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x96200470)

        elif (DDR_CLK < DDR2133_TH):
            # 1866
#           CCSR_LE_M(0x0000000001080100 + id * 0x10000, 0x010e1100)
#           CCSR_LE_M(0x0000000001080104 + id * 0x10000, 0x90660018)
#           CCSR_LE_M(0x0000000001080108 + id * 0x10000, 0xdfd8b045)
#           CCSR_LE_M(0x000000000108010c + id * 0x10000, 0x00512154)
            CCSR_LE_M(0x0000000001080100 + id * 0x10000, 0x01131100)
            CCSR_LE_M(0x0000000001080104 + id * 0x10000, 0x91660018)
            CCSR_LE_M(0x0000000001080108 + id * 0x10000, 0xded8f045)
            CCSR_LE_M(0x000000000108010c + id * 0x10000, 0x00512154)
            
#           CCSR_LE_M(0x0000000001080160 + id * 0x10000, 0x00220002)
#           CCSR_LE_M(0x0000000001080164 + id * 0x10000, 0x04401400)
#           CCSR_LE_M(0x0000000001080168 + id * 0x10000, 0x00000000)
#           CCSR_LE_M(0x000000000108016c + id * 0x10000, 0x15500000)
            CCSR_LE_M(0x0000000001080160 + id * 0x10000, 0x00220002)
            CCSR_LE_M(0x0000000001080164 + id * 0x10000, 0x04401400)
            CCSR_LE_M(0x0000000001080168 + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x000000000108016c + id * 0x10000, 0x25500000)
            
#           CCSR_LE_M(0x0000000001080250 + id * 0x10000, 0x03335900)
            CCSR_LE_M(0x0000000001080250 + id * 0x10000, 0x03335900)

#           CCSR_LE_M(0x0000000001080118 + id * 0x10000, 0x03010421)
#           CCSR_LE_M(0x000000000108011c + id * 0x10000, 0x00080200)
            CCSR_LE_M(0x0000000001080110 + id * 0x10000, 0xE5004000)
            CCSR_LE_M(0x0000000001080114 + id * 0x10000, 0x00401141)
            CCSR_LE_M(0x0000000001080118 + id * 0x10000, 0x03010421)
            CCSR_LE_M(0x000000000108011c + id * 0x10000, 0x00080200)

#           CCSR_LE_M(0x0000000001080200 + id * 0x10000, 0x00010421)
#           CCSR_LE_M(0x0000000001080204 + id * 0x10000, 0x00080200)
#           CCSR_LE_M(0x0000000001080208 + id * 0x10000, 0x00010421)
#           CCSR_LE_M(0x000000000108020c + id * 0x10000, 0x00080200)
#           CCSR_LE_M(0x0000000001080210 + id * 0x10000, 0x00010421)
#           CCSR_LE_M(0x0000000001080214 + id * 0x10000, 0x00080200)
            CCSR_LE_M(0x0000000001080200 + id * 0x10000, 0x00010421)
            CCSR_LE_M(0x0000000001080204 + id * 0x10000, 0x00080200)
            CCSR_LE_M(0x0000000001080208 + id * 0x10000, 0x00010421)
            CCSR_LE_M(0x000000000108020c + id * 0x10000, 0x00080200)
            CCSR_LE_M(0x0000000001080210 + id * 0x10000, 0x00010421)
            CCSR_LE_M(0x0000000001080214 + id * 0x10000, 0x00080200)

#           CCSR_LE_M(0x0000000001080220 + id * 0x10000, 0x00000500)
#           CCSR_LE_M(0x0000000001080224 + id * 0x10000, 0x04000000)
#           CCSR_LE_M(0x0000000001080228 + id * 0x10000, 0x00000400)
#           CCSR_LE_M(0x000000000108022c + id * 0x10000, 0x04000000)
#           CCSR_LE_M(0x0000000001080230 + id * 0x10000, 0x00000400)
#           CCSR_LE_M(0x0000000001080234 + id * 0x10000, 0x04000000)
#           CCSR_LE_M(0x0000000001080238 + id * 0x10000, 0x00000400)
#           CCSR_LE_M(0x000000000108023c + id * 0x10000, 0x04000000)
            CCSR_LE_M(0x0000000001080220 + id * 0x10000, 0x00000500)
            CCSR_LE_M(0x0000000001080224 + id * 0x10000, 0x04000000)
            CCSR_LE_M(0x0000000001080228 + id * 0x10000, 0x00000400)
            CCSR_LE_M(0x000000000108022c + id * 0x10000, 0x04000000)
            CCSR_LE_M(0x0000000001080230 + id * 0x10000, 0x00000400)
            CCSR_LE_M(0x0000000001080234 + id * 0x10000, 0x04000000)
            CCSR_LE_M(0x0000000001080238 + id * 0x10000, 0x00000400)
            CCSR_LE_M(0x000000000108023c + id * 0x10000, 0x04000000)
            
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x0000000001080124 + id * 0x10000, 0x1c700100)
            CCSR_LE_M(0x0000000001080174 + id * 0x10000, 0x8675f607)
            CCSR_LE_M(0x0000000001080190 + id * 0x10000, 0x09090b0d)
            CCSR_LE_M(0x0000000001080194 + id * 0x10000, 0x0e10120b)

            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x862004c0)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x862004f0)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x86200470)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x962004c0)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x962004f0)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x96200470)

        else:
            # 2133
            CCSR_LE_M(0x0000000001080100 + id * 0x10000, 0x02101100)
            CCSR_LE_M(0x0000000001080104 + id * 0x10000, 0xd0770018)
            CCSR_LE_M(0x0000000001080108 + id * 0x10000, 0xf4fce245)
            CCSR_LE_M(0x000000000108010c + id * 0x10000, 0x00594197)
            CCSR_LE_M(0x0000000001080160 + id * 0x10000, 0x00220002)
            CCSR_LE_M(0x0000000001080164 + id * 0x10000, 0x05401400)
            CCSR_LE_M(0x0000000001080168 + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x000000000108016c + id * 0x10000, 0x26600000)
            CCSR_LE_M(0x0000000001080250 + id * 0x10000, 0x05446a00)

            CCSR_LE_M(0x0000000001080118 + id * 0x10000, 0x03010631)
            CCSR_LE_M(0x000000000108011c + id * 0x10000, 0x00100200)
            CCSR_LE_M(0x0000000001080200 + id * 0x10000, 0x00010631)
            CCSR_LE_M(0x0000000001080204 + id * 0x10000, 0x00100200)
            CCSR_LE_M(0x0000000001080208 + id * 0x10000, 0x00010631)
            CCSR_LE_M(0x000000000108020c + id * 0x10000, 0x00100200)
            CCSR_LE_M(0x0000000001080210 + id * 0x10000, 0x00010631)
            CCSR_LE_M(0x0000000001080214 + id * 0x10000, 0x00100200)
            CCSR_LE_M(0x0000000001080220 + id * 0x10000, 0x00000500)
            CCSR_LE_M(0x0000000001080224 + id * 0x10000, 0x08000000)
            CCSR_LE_M(0x0000000001080228 + id * 0x10000, 0x00000400)
            CCSR_LE_M(0x000000000108022c + id * 0x10000, 0x08000000)
            CCSR_LE_M(0x0000000001080230 + id * 0x10000, 0x00000400)
            CCSR_LE_M(0x0000000001080234 + id * 0x10000, 0x08000000)
            CCSR_LE_M(0x0000000001080238 + id * 0x10000, 0x00000400)
            CCSR_LE_M(0x000000000108023c + id * 0x10000, 0x08000000)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x00000000)
            CCSR_LE_M(0x0000000001080124 + id * 0x10000, 0x20800100)
            CCSR_LE_M(0x0000000001080174 + id * 0x10000, 0x8675f608)
            CCSR_LE_M(0x0000000001080190 + id * 0x10000, 0x090a0c0f)
            CCSR_LE_M(0x0000000001080194 + id * 0x10000, 0x1012130c)

            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x862008c0)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x862008f0)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x86200870)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x962008c0)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x962008f0)
            CCSR_LE_M(0x0000000001080120 + id * 0x10000, 0x96200870)

        CCSR_LE_M(0x0000000001080254 + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x0000000001080170 + id * 0x10000, 0x8a090705)
        CCSR_LE_M(0x0000000001080400 + id * 0x10000, 0x32c57554)
        CCSR_LE_M(0x0000000001080404 + id * 0x10000, 0xd4bb0bd4)
        CCSR_LE_M(0x0000000001080408 + id * 0x10000, 0x2ec2f554)
        CCSR_LE_M(0x000000000108040c + id * 0x10000, 0xd95d4001)
        CCSR_LE_M(0x0000000001080260 + id * 0x10000, 0x00000000)

        CCSR_LE_M(0x0000000001080128 + id * 0x10000, 0xdeadbeef)
        CCSR_LE_M(0x000000000108017c + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x0000000001080180 + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x0000000001080184 + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x00000000010801a0 + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x00000000010801a4 + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x00000000010801a8 + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x00000000010801ac + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x0000000001080b28 + id * 0x10000, 0x80040000)
        CCSR_LE_M(0x0000000001080114 + id * 0x10000, 0x00401151)
        CCSR_LE_M(0x0000000001080148 + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x000000000108014c + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x0000000001080b2c + id * 0x10000, 0x0000a181)
        CCSR_LE_M(0x0000000001080e44 + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x0000000001080e48 + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x0000000001080b2c + id * 0x10000, 0x0000a101)
        CCSR_LE_M(0x0000000001080f70 + id * 0x10000, 0x00000400)
        CCSR_LE_M(0x0000000001080114 + id * 0x10000, 0x00401141)
        CCSR_LE_M(0x0000000001080110 + id * 0x10000, 0x65004000)
        CCSR_LE_M(0x0000000001080110 + id * 0x10000, 0xe5004000)

        CCSR_LE_M(0x0000000001080f70 + id * 0x10000, 0x00000000)
        CCSR_LE_M(0x0000000001080f04 + id * 0x10000, 0x00000400)

        count = 0
        while True:
            time.sleep(0.2)
            controller_idle = CCSR_LE_D(0x0000000001080f04 + id * 0x10000) & 0x00000002
            count = count + 1
            if (controller_idle != 0x00000000):
                break
            if (count > 10):
                break

        CCSR_LE_M(0x0000000001080114 + id * 0x10000, 0x00401151)
        count = 0
        while True:
            time.sleep(0.2)
            SDRAM_CFG2 = CCSR_LE_D(0x0000000001080114 + id * 0x10000)
            D_INIT = SDRAM_CFG2 & 0x10
            count = count + 1
            if (D_INIT == 0):
                break
            if (count > 10):
                print "DDRC1: Time out waiting for D_INIT on DDRC", (id + 1)
                break

        ERR_DETECT = CCSR_LE_D(0x0000000001080E40 + id * 0x10000)

        if (ERR_DETECT != 0):
            print "Memory initialization error on DDRC!", (id + 1)
            print format(ERR_DETECT, '08x')

def Init_DPDDRC(DDR_CLK):

    DDR1600_TH = 1450

    CCSR_LE_M(0x0000000700132800, 0x63b20002)

    CCSR_LE_M(0x0000000008210130, 0x02000000)
    CCSR_LE_M(0x0000000008210000, 0x000000ff)
    CCSR_LE_M(0x0000000008210080, 0x80050322)
    CCSR_LE_M(0x00000000082100c0, 0x00000000)
    CCSR_LE_M(0x0000000008210008, 0x000000ff)
    CCSR_LE_M(0x0000000008210084, 0x80000322)
    CCSR_LE_M(0x00000000082100c4, 0x00000000)
    CCSR_LE_M(0x0000000008210010, 0x00000000)
    CCSR_LE_M(0x0000000008210088, 0x00000000)
    CCSR_LE_M(0x00000000082100c8, 0x00000000)
    CCSR_LE_M(0x0000000008210018, 0x00000000)
    CCSR_LE_M(0x000000000821008c, 0x00000000)
    CCSR_LE_M(0x00000000082100cc, 0x00000000)

    if (DDR_CLK < DDR1600_TH):
        # 1333
        CCSR_LE_M(0x0000000008210100, 0x010a1000)
        CCSR_LE_M(0x0000000008210104, 0x90440018)
        CCSR_LE_M(0x0000000008210108, 0x96906a42)
        CCSR_LE_M(0x000000000821010c, 0x0048a10e)
        CCSR_LE_M(0x0000000008210160, 0x00000002)
        CCSR_LE_M(0x0000000008210164, 0x01401400)
        CCSR_LE_M(0x0000000008210168, 0x00000000)
        CCSR_LE_M(0x000000000821016c, 0x02200000)
        CCSR_LE_M(0x0000000008210250, 0x00004500)

        CCSR_LE_M(0x0000000008210118, 0x03010000)
        CCSR_LE_M(0x000000000821011c, 0x00000000)
        CCSR_LE_M(0x0000000008210200, 0x00010000)
        CCSR_LE_M(0x0000000008210204, 0x00000000)
        CCSR_LE_M(0x0000000008210208, 0x00010000)
        CCSR_LE_M(0x000000000821020c, 0x00000000)
        CCSR_LE_M(0x0000000008210210, 0x00010000)
        CCSR_LE_M(0x0000000008210214, 0x00000000)
        CCSR_LE_M(0x0000000008210220, 0x00000500)
        CCSR_LE_M(0x0000000008210224, 0x00000000)
        CCSR_LE_M(0x0000000008210228, 0x00000400)
        CCSR_LE_M(0x000000000821022c, 0x00000000)
        CCSR_LE_M(0x0000000008210230, 0x00000400)
        CCSR_LE_M(0x0000000008210234, 0x00000000)
        CCSR_LE_M(0x0000000008210238, 0x00000400)
        CCSR_LE_M(0x000000000821023c, 0x00000000)
        CCSR_LE_M(0x0000000008210120, 0x00000000)
        CCSR_LE_M(0x0000000008210124, 0x14500000)
    else:
        #1600
        CCSR_LE_M(0x0000000008210100, 0x010c1000)
        CCSR_LE_M(0x0000000008210104, 0x90550018)
        CCSR_LE_M(0x0000000008210108, 0xbbb48c42)
        CCSR_LE_M(0x000000000821010c, 0x0048c111)
        CCSR_LE_M(0x0000000008210160, 0x00000002)
        CCSR_LE_M(0x0000000008210164, 0x03401400)
        CCSR_LE_M(0x0000000008210168, 0x00000000)
        CCSR_LE_M(0x000000000821016c, 0x13300000)
        CCSR_LE_M(0x0000000008210250, 0x02115600)

        CCSR_LE_M(0x0000000008210118, 0x03010210)
        CCSR_LE_M(0x000000000821011c, 0x00000000)
        CCSR_LE_M(0x0000000008210200, 0x00010210)
        CCSR_LE_M(0x0000000008210204, 0x00000000)
        CCSR_LE_M(0x0000000008210208, 0x00010210)
        CCSR_LE_M(0x000000000821020c, 0x00000000)
        CCSR_LE_M(0x0000000008210210, 0x00010210)
        CCSR_LE_M(0x0000000008210214, 0x00000000)
        CCSR_LE_M(0x0000000008210220, 0x00000500)
        CCSR_LE_M(0x0000000008210224, 0x04000000)
        CCSR_LE_M(0x0000000008210228, 0x00000400)
        CCSR_LE_M(0x000000000821022c, 0x04000000)
        CCSR_LE_M(0x0000000008210230, 0x00000400)
        CCSR_LE_M(0x0000000008210234, 0x04000000)
        CCSR_LE_M(0x0000000008210238, 0x00000400)
        CCSR_LE_M(0x000000000821023c, 0x04000000)
        CCSR_LE_M(0x0000000008210120, 0x00000000)
        CCSR_LE_M(0x0000000008210124, 0x18600000)

    CCSR_LE_M(0x0000000008210254, 0x00000000)
    CCSR_LE_M(0x0000000008210170, 0x8a090705)
    CCSR_LE_M(0x0000000008210400, 0x5752ec54)
    CCSR_LE_M(0x0000000008210404, 0xd55d4000)
    CCSR_LE_M(0x0000000008210408, 0x00000000)
    CCSR_LE_M(0x000000000821040c, 0x00c00001)
    CCSR_LE_M(0x0000000008210260, 0x00000000)

    CCSR_LE_M(0x0000000008210128, 0xdeadbeef)
    CCSR_LE_M(0x0000000008210174, 0x8675f60d)
    CCSR_LE_M(0x0000000008210190, 0x0c0a0a00)
    CCSR_LE_M(0x0000000008210194, 0x00000009)
    CCSR_LE_M(0x000000000821017c, 0x00000000)
    CCSR_LE_M(0x0000000008210180, 0x00000000)
    CCSR_LE_M(0x0000000008210184, 0x00000000)
    CCSR_LE_M(0x00000000082101a0, 0x00000000)
    CCSR_LE_M(0x00000000082101a4, 0x00000000)
    CCSR_LE_M(0x00000000082101a8, 0x00000000)
    CCSR_LE_M(0x00000000082101ac, 0x00000000)
    CCSR_LE_M(0x0000000008210b28, 0x80040000)
    CCSR_LE_M(0x0000000008210114, 0x00401111)
    CCSR_LE_M(0x0000000008210148, 0x00000000)
    CCSR_LE_M(0x000000000821014c, 0x00000000)
    CCSR_LE_M(0x0000000008210b2c, 0x0000a181)
    CCSR_LE_M(0x0000000008210e44, 0x00000000)
    CCSR_LE_M(0x0000000008210e48, 0x00000000)
    CCSR_LE_M(0x0000000008210110, 0x650c4004)
    CCSR_LE_M(0x0000000008210110, 0xe50c4004)

    count = 0
    while True:
        time.sleep(0.2)
        SDRAM_CFG2 = CCSR_LE_D(0x0000000008210114)
        D_INIT = SDRAM_CFG2 & 0x10
        count = count + 1
        if (D_INIT == 0):
            break
        if (count > 20):
            print "DPDDRC: Time out waiting for D_INIT on DPDDRC"
            break

    ERR_DETECT = CCSR_LE_D(0x0000000008210E40)

    if (ERR_DETECT != 0):
        print "Memory initialization error on DPDDRC!"
        print format(ERR_DETECT, '08x')

###################################################################
# Detect DDR frequency
###################################################################
def Detect_DDR_Freq():
    # Detect DDR data rate from RCWSR1 (DDRCLK is fixed at 133.33MHz)
    DDRCLK = 133.33

    RCWSR1 = CCSR_LE_D(0x01e00100)
    MEM_PLL_RAT = (RCWSR1 >> 10) & 0x3F
    MEM2_PLL_RAT = (RCWSR1 >> 18) & 0x3F

    DDR_freq = int(round(MEM_PLL_RAT * DDRCLK))
    DPDDR_freq = int(round(MEM2_PLL_RAT * DDRCLK))

    return  DDR_freq, DPDDR_freq

###################################################################
# IFC Initialization
###################################################################
def Init_IFC():

    # Disable CSPR0
    CCSR_LE_M(0x02240010, 0x00000000)

    # Init CPLD first, and read CS mapping from there
    CPLD_CS = 3

    # CSPR_EXT
    CCSR_LE_M(0x0224000C + CPLD_CS * 12, 0x00000000)
    # CSPR
    CCSR_LE_M(0x02240010 + CPLD_CS * 12, CPLD_ADDR | 0x85)
    # AMASK
    CCSR_LE_M(0x022400A0 + CPLD_CS * 12, 0xFFFF0000)
    # CSOR
    CCSR_LE_M(0x02240130 + CPLD_CS * 12, 0x00018000)

    # IFC_FTIM0
    CCSR_LE_M(0x022401C0 + CPLD_CS * 48, 0xe00e000e)
    # IFC_FTIM1
    CCSR_LE_M(0x022401C4 + CPLD_CS * 48, 0xff003f00)
    # IFC_FTIM2
    CCSR_LE_M(0x022401C8 + CPLD_CS * 48, 0x0f3c003e)
    # IFC_FTIM3
    CCSR_LE_M(0x022401CC + CPLD_CS * 48, 0x00000000)

    SYS_ID = FPGA_D(0x00)
    if (SYS_ID != 0x35):
        print "FPGA not detected, using default CS mapping"
        NOR_CS = 0
        NAND_CS = 2
    else:
        # LBMAP = BRDCFG[3:0]
        LBMAP = FPGA_D(0x50) & 0X0F
        if (LBMAP < 8):
            NOR_CS = 0
            NAND_CS = 2
        else:
            NAND_CS = 0
            NOR_CS = 2

    # CSPR_EXT
    CCSR_LE_M(0x0224000C + NOR_CS * 12, 0x00000000)
    # CSPR
    CCSR_LE_M(0x02240010 + NOR_CS * 12, 0x80000101)
    # AMASK
    CCSR_LE_M(0x022400A0 + NOR_CS * 12, 0xF8000000)
    # CSOR
    CCSR_LE_M(0x02240130 + NOR_CS * 12, 0x00018000)

    # IFC_FTIM0
    CCSR_LE_M(0x022401C0 + NOR_CS * 48, 0x40050005)
    # IFC_FTIM1
    CCSR_LE_M(0x022401C4 + NOR_CS * 48, 0x35001A13)
    # IFC_FTIM2
    CCSR_LE_M(0x022401C8 + NOR_CS * 48, 0x0410381C)
    # IFC_FTIM3
    CCSR_LE_M(0x022401CC + NOR_CS * 48, 0x04000000)

    # CSPR_EXT
    CCSR_LE_M(0x0224000C + NAND_CS * 12, 0x00000000)
    # CSPR
    CCSR_LE_M(0x02240010 + NAND_CS * 12, 0x08000083)
    # AMASK
    CCSR_LE_M(0x022400A0 + NAND_CS * 12, 0xFFFF0000)
    # CSOR
    CCSR_LE_M(0x02240130 + NAND_CS * 12, 0x8510A200)

    # IFC_FTIM0
    CCSR_LE_M(0x022401C0 + NAND_CS * 48, 0x1c300e14)
    # IFC_FTIM1
    CCSR_LE_M(0x022401C4 + NAND_CS * 48, 0x64ab1c30)
    # IFC_FTIM2
    CCSR_LE_M(0x022401C8 + NAND_CS * 48, 0x03c0a03c)
    # IFC_FTIM3
    CCSR_LE_M(0x022401CC + NAND_CS * 48, 0x00000000)

###################################################################
# QSPI Initialization
###################################################################
def Init_QSPI():
    # QuadSPI_MCR - disable device clocks
    CCSR_LE_M(0x20C0000, 0x000F0000)

    # SMPR
    CCSR_LE_M(0x20C0108, 0x00000000)

    # QuadSPI_MCR - enable device clocks
    CCSR_LE_M(0x20C0000, 0x000F4000)

    # QuadSPI_FLSHCR
    CCSR_LE_M(0x20C000C, 0x00000303)

    # Set top address for each device
    CCSR_LE_M(0x20C0180, 0x24000000)
    CCSR_LE_M(0x20C0184, 0x28000000)

    # BUF0CR
    CCSR_LE_M(0x20C0010, 0x00000000)
    # BUF3CR
    CCSR_LE_M(0x20C001C, 0x80000000)
    # BFGENCR
    CCSR_LE_M(0x20C0020, 0x00000000)

    # SCFG_QSPICLKCTLR
    CCSR_LE_M(0x1FC0010, 0x40000000)

###################################################################
# SD Initialization
###################################################################
def Init_ESDHC():
    # CS[0:3]_B connect to SDCard as SD_DAT[4:7]
    FPGA_M(0x55, 0x0)
    # Assert PORESET_B to DUT to start normal reset sequence
    FPGA_M(0x40, 0x30)

###################################################################
# Cache Coherent Interconnect (CCN-504) Initialization
###################################################################
def Init_CCI():

    # Use MN to read the available RN-F, RN-D and HN-F nodes
    RNF = CCSR_LE_D(0x04000000 + 0x180)
    RND = CCSR_LE_D(0x04000000 + 0x1A0)
    HNF = CCSR_LE_D(0x04000000 + 0x1B0)

    # Add RNFs and RNDs to the DVM domain (in MN)
    CCSR_LE_M(0x04000000 + 0x210, RNF | RND)

    # Add RNFs to each HNF's snoop domain
    for region in range(bin(HNF).count('1')):
        CCSR_LE_M(0x04200000 + region * 0x10000 + 0x210, RNF)

###################################################################
# Adds Flash devices for this board
###################################################################
def Config_Flash_Devices():
    fl = flash.create(TA)

    if QSPI_BOOT:
        # Add QSPI device
        fl.add_device({"alias": "qspi", "name": "S25FS512S", "address": 0x20000000, "ws_address": 0x18000000, "ws_size": 0x1FFFF, "geometry": "8x1", "controller": "QSPI"})
    else:
        # Add NAND device
        fl.add_device({"alias": "nand", "name": "MT29F16G08ABABA", "address": 0x38000000, "ws_address": 0x18000000, "ws_size": 0x1FFFF, "geometry": "8x1", "controller": "IFC"})

        # Add NOR device
        fl.add_device({"alias": "nor", "name": "S29GL01GP", "address": 0x580000000, "ws_address": 0x18000000, "ws_size": 0x1FFFF, "geometry": "16x1", "controller": "IFC"})

    # Add SD/eMMC device
    fl.add_device({"alias": "sd", "name": "SDSP16GB_LSCH3_v2", "address": 0x00000000, "ws_address": 0x80000000, "ws_size": 0x1FFFF, "geometry": "8x1", "controller": "eSDHC"})

    if QSPI_BOOT:
        # Set QSPI as current device
        fl.set_current_device("qspi")
    else:
        # Set NOR as current device
        fl.set_current_device("nor")

###################################################################
# This is the actual function called by debugger, flash, etc.
###################################################################
def run_init_file():
    Prepare_Env()

    # Reset with RCW override option (USE_SAFE_RCW)
    Reset()

    # Because the QSPI controller cannot work at the same time with
    # the IFC controller, only the used controller is initialized.
    if QSPI_BOOT:
        Init_QSPI()
    else:
        Init_IFC()
    Init_ESDHC()

    Init_TZASC()

    DDR_freq, DPDDR_freq = Detect_DDR_Freq()
    print "DDR frequency is: ", DDR_freq
    print "AIOP DDR frequency is: ", DPDDR_freq
    Init_DDRC(DDR_freq)
    Init_DPDDRC(DPDDR_freq)

    Init_CCI()

    Config_Flash_Devices()

 

DDR1	0x1080000	
CS0_BNDS	0x000007ff	0x0	RW	0x1080000	Chip select 0 memory bounds	
CS1_BNDS	0x000007ff	0x0	RW	0x1080008	Chip select 1 memory bounds	
CS2_BNDS	0x00000000	0x0	RW	0x1080010	Chip select 2 memory bounds	
CS3_BNDS	0x00000000	0x0	RW	0x1080018	Chip select 3 memory bounds	
CS0_CONFIG	0xa8050422	0x0	RW	0x1080080	Chip select 0 configuration	
CS1_CONFIG	0x80000422	0x0	RW	0x1080084	Chip select 1 configuration	
CS2_CONFIG	0x00000000	0x0	RW	0x1080088	Chip select 2 configuration	
CS3_CONFIG	0x00000000	0x0	RW	0x108008c	Chip select 3 configuration	
CS0_CONFIG_2	0x00000000	0x0	RW	0x10800c0	Chip select 0 configuration 2	
CS1_CONFIG_2	0x00000000	0x0	RW	0x10800c4	Chip select 1 configuration 2	
CS2_CONFIG_2	0x00000000	0x0	RW	0x10800c8	Chip select 2 configuration 2	
CS3_CONFIG_2	0x00000000	0x0	RW	0x10800cc	Chip select 3 configuration 2	
TIMING_CFG_3	0x01131100	0x0	RW	0x1080100	DDR SDRAM timing configuration 3	
TIMING_CFG_0	0x91660018	0x110005	RW	0x1080104	DDR SDRAM timing configuration 0	
TIMING_CFG_1	0xded8f045	0x0	RW	0x1080108	DDR SDRAM timing configuration 1	
TIMING_CFG_2	0x00512154	0x0	RW	0x108010c	DDR SDRAM timing configuration 2	
DDR_SDRAM_CFG	0xe5004000	0x7000000	RW	0x1080110	DDR SDRAM control configuration	
DDR_SDRAM_CFG_2	0x00401141	0x0	RW	0x1080114	DDR SDRAM control configuration 2	
DDR_SDRAM_MODE	0x03010421	0x0	RW	0x1080118	DDR SDRAM mode configuration	
DDR_SDRAM_MODE_2	0x00080200	0x0	RW	0x108011c	DDR SDRAM mode configuration 2	
DDR_SDRAM_MD_CNTL	0x1600046b	0x0	RW	0x1080120	DDR SDRAM mode control	
DDR_SDRAM_INTERVAL	0x1c70071c	0x0	RW	0x1080124	DDR SDRAM interval configuration	
DDR_DATA_INIT	0xdeadbeef	0x0	RW	0x1080128	DDR SDRAM data initialization	
DDR_SDRAM_CLK_CNTL	0x03000000	0x2000000	RW	0x1080130	DDR SDRAM clock control	
DDR_INIT_ADDR	0x00000000	0x0	RW	0x1080148	DDR training initialization address	
DDR_INIT_EXT_ADDRESS	0x00000000	0x0	RW	0x108014c	DDR training initialization extended address	
TIMING_CFG_4	0x00220002	0x0	RW	0x1080160	DDR SDRAM timing configuration 4	
TIMING_CFG_5	0x04401400	0x0	RW	0x1080164	DDR SDRAM timing configuration 5	
TIMING_CFG_7	0x25500000	0x0	RW	0x108016c	DDR SDRAM timing configuration 7	
DDR_ZQ_CNTL	0x8a090705	0x0	RW	0x1080170	DDR ZQ calibration control	
DDR_WRLVL_CNTL	0xc675060a	0x0	RW	0x1080174	DDR write leveling control	
DDR_SR_CNTR	0x00000000	0x0	RW	0x108017c	DDR Self Refresh Counter	
DDR_SDRAM_RCW_1	0x00000000	0x0	RW	0x1080180	DDR Register Control Words 1	
DDR_SDRAM_RCW_2	0x00000000	0x0	RW	0x1080184	DDR Register Control Words 2	
DDR_WRLVL_CNTL_2	0x0b0c0e11	0x0	RW	0x1080190	DDR write leveling control 2	
DDR_WRLVL_CNTL_3	0x1214140f	0x0	RW	0x1080194	DDR write leveling control 3	
DDR_SDRAM_RCW_3	0x00000000	0x0	RW	0x10801a0	DDR Register Control Words 3	
DDR_SDRAM_RCW_4	0x00000000	0x0	RW	0x10801a4	DDR Register Control Words 4	
DDR_SDRAM_RCW_5	0x00000000	0x0	RW	0x10801a8	DDR Register Control Words 5	
DDR_SDRAM_RCW_6	0x00000000	0x0	RW	0x10801ac	DDR Register Control Words 6	
DDR_SDRAM_MODE_3	0x00010421	0x0	RW	0x1080200	DDR SDRAM mode configuration 3	
DDR_SDRAM_MODE_4	0x00080200	0x0	RW	0x1080204	DDR SDRAM mode configuration 4	
DDR_SDRAM_MODE_5	0x00010421	0x0	RW	0x1080208	DDR SDRAM mode configuration 5	
DDR_SDRAM_MODE_6	0x00080200	0x0	RW	0x108020c	DDR SDRAM mode configuration 6	
DDR_SDRAM_MODE_7	0x00010421	0x0	RW	0x1080210	DDR SDRAM mode configuration 7	
DDR_SDRAM_MODE_8	0x00080200	0x0	RW	0x1080214	DDR SDRAM mode configuration 8	
DDR_SDRAM_MODE_9	0x00000500	0x0	RW	0x1080220	DDR SDRAM mode configuration 9	
DDR_SDRAM_MODE_10	0x04400000	0x0	RW	0x1080224	DDR SDRAM mode configuration 10	
DDR_SDRAM_MODE_11	0x00000400	0x0	RW	0x1080228	DDR SDRAM mode configuration 11	
DDR_SDRAM_MODE_12	0x04400000	0x0	RW	0x108022c	DDR SDRAM mode configuration 12	
DDR_SDRAM_MODE_13	0x00000400	0x0	RW	0x1080230	DDR SDRAM mode configuration 13	
DDR_SDRAM_MODE_14	0x04400000	0x0	RW	0x1080234	DDR SDRAM mode configuration 14	
DDR_SDRAM_MODE_15	0x00000400	0x0	RW	0x1080238	DDR SDRAM mode configuration 15	
DDR_SDRAM_MODE_16	0x04400000	0x0	RW	0x108023c	DDR SDRAM mode configuration 16	
TIMING_CFG_8	0x03335900	0x0	RW	0x1080250	DDR SDRAM timing configuration 8	
DDR_SDRAM_CFG_3	0x00000000	0x0	RW	0x1080260	DDR SDRAM control configuration 3	
DDR_DQ_MAP0	0x32c57554	0x0	RW	0x1080400	DQ mapping register 0	
DDR_DQ_MAP1	0xd4bb0bd4	0x0	RW	0x1080404	DQ mapping register 1	
DDR_DQ_MAP2	0x2ec2f554	0x0	RW	0x1080408	DQ mapping register 2	
DDR_DQ_MAP3	0xd95d4001	0x0	RW	0x108040c	DQ mapping register 3	
DDRDSR_1	0x00008080	0x8080	R	0x1080b20	DDR Debug Status Register 1	
DDRDSR_2	0x80000000	0x80000000	RW	0x1080b24	DDR Debug Status Register 2	
DDRCDR_1	0x80080000	0x0	RW	0x1080b28	DDR Control Driver Register 1	
DDRCDR_2	0x000000c0	0x0	RW	0x1080b2c	DDR Control Driver Register 2	
DDR_IP_REV1	0x00020502	0x20502	R	0x1080bf8	DDR IP block revision 1	
DDR_IP_REV2	0x00000100	0x0	R	0x1080bfc	DDR IP block revision 2	
DDR_MTCR	0x00000000	0x0	RW	0x1080d00	DDR Memory Test Control Register	
DDR_MTP1	0x00000000	0x0	RW	0x1080d20	DDR Memory Test Pattern n Register	
DDR_MTP2	0x00000000	0x0	RW	0x1080d24	DDR Memory Test Pattern n Register	
DDR_MTP3	0x00000000	0x0	RW	0x1080d28	DDR Memory Test Pattern n Register	
DDR_MTP4	0x00000000	0x0	RW	0x1080d2c	DDR Memory Test Pattern n Register	
DDR_MTP5	0x00000000	0x0	RW	0x1080d30	DDR Memory Test Pattern n Register	
DDR_MTP6	0x00000000	0x0	RW	0x1080d34	DDR Memory Test Pattern n Register	
DDR_MTP7	0x00000000	0x0	RW	0x1080d38	DDR Memory Test Pattern n Register	
DDR_MTP8	0x00000000	0x0	RW	0x1080d3c	DDR Memory Test Pattern n Register	
DDR_MTP9	0x00000000	0x0	RW	0x1080d40	DDR Memory Test Pattern n Register	
DDR_MTP10	0x00000000	0x0	RW	0x1080d44	DDR Memory Test Pattern n Register	
DDR_MT_ST_EXT_ADDR	0x00000000	0x0	RW	0x1080d60	DDR Memory Test Start Extended Address	
DDR_MT_ST_ADDR	0x00000000	0x0	RW	0x1080d64	DDR Memory Test Start Address	
DDR_MT_END_EXT_ADDR	0x00000000	0x0	RW	0x1080d68	DDR Memory Test End Extended Address	
DDR_MT_END_ADDR	0x00000000	0x0	RW	0x1080d6c	DDR Memory Test End Address	
DATA_ERR_INJECT_HI	0x00000000	0x0	RW	0x1080e00	Memory data path error injection mask high	
DATA_ERR_INJECT_LO	0x00000000	0x0	RW	0x1080e04	Memory data path error injection mask low	
ECC_ERR_INJECT	0x00000000	0x0	RW	0x1080e08	Memory data path error injection mask ECC	
CAPTURE_DATA_HI	0x00000000	0x0	RW	0x1080e20	Memory data path read capture high	
CAPTURE_DATA_LO	0x00000000	0x0	RW	0x1080e24	Memory data path read capture low	
CAPTURE_ECC	0x00000000	0x0	RW	0x1080e28	Memory data path read capture ECC	
ERR_DETECT	0x00000000	0x0	RW	0x1080e40	Memory error detect	
ERR_DISABLE	0x00000000	0x0	RW	0x1080e44	Memory error disable	
ERR_INT_EN	0x00000000	0x0	RW	0x1080e48	Memory error interrupt enable	
CAPTURE_ATTRIBUTES	0x00000000	0x0	RW	0x1080e4c	Memory error attributes capture	
CAPTURE_ADDRESS	0x00000000	0x0	RW	0x1080e50	Memory error address capture	
CAPTURE_EXT_ADDRESS	0x00000000	0x0	RW	0x1080e54	Memory error extended address capture	
ERR_SBE	0x00000000	0x0	RW	0x1080e58	Single-Bit ECC memory error management	
DDR2	0x1090000	
CS0_BNDS	0x000007ff	0x0	RW	0x1090000	Chip select 0 memory bounds	
CS1_BNDS	0x000007ff	0x0	RW	0x1090008	Chip select 1 memory bounds	
CS2_BNDS	0x00000000	0x0	RW	0x1090010	Chip select 2 memory bounds	
CS3_BNDS	0x00000000	0x0	RW	0x1090018	Chip select 3 memory bounds	
CS0_CONFIG	0xa8050422	0x0	RW	0x1090080	Chip select 0 configuration	
CS1_CONFIG	0x80000422	0x0	RW	0x1090084	Chip select 1 configuration	
CS2_CONFIG	0x00000000	0x0	RW	0x1090088	Chip select 2 configuration	
CS3_CONFIG	0x00000000	0x0	RW	0x109008c	Chip select 3 configuration	
CS0_CONFIG_2	0x00000000	0x0	RW	0x10900c0	Chip select 0 configuration 2	
CS1_CONFIG_2	0x00000000	0x0	RW	0x10900c4	Chip select 1 configuration 2	
CS2_CONFIG_2	0x00000000	0x0	RW	0x10900c8	Chip select 2 configuration 2	
CS3_CONFIG_2	0x00000000	0x0	RW	0x10900cc	Chip select 3 configuration 2	
TIMING_CFG_3	0x01131100	0x0	RW	0x1090100	DDR SDRAM timing configuration 3	
TIMING_CFG_0	0x91660018	0x110005	RW	0x1090104	DDR SDRAM timing configuration 0	
TIMING_CFG_1	0xded8f045	0x0	RW	0x1090108	DDR SDRAM timing configuration 1	
TIMING_CFG_2	0x00512154	0x0	RW	0x109010c	DDR SDRAM timing configuration 2	
DDR_SDRAM_CFG	0xe5004000	0x7000000	RW	0x1090110	DDR SDRAM control configuration	
DDR_SDRAM_CFG_2	0x00401141	0x0	RW	0x1090114	DDR SDRAM control configuration 2	
DDR_SDRAM_MODE	0x03010421	0x0	RW	0x1090118	DDR SDRAM mode configuration	
DDR_SDRAM_MODE_2	0x00080200	0x0	RW	0x109011c	DDR SDRAM mode configuration 2	
DDR_SDRAM_MD_CNTL	0x1600046b	0x0	RW	0x1090120	DDR SDRAM mode control	
DDR_SDRAM_INTERVAL	0x1c700000	0x0	RW	0x1090124	DDR SDRAM interval configuration	
DDR_DATA_INIT	0xdeadbeef	0x0	RW	0x1090128	DDR SDRAM data initialization	
DDR_SDRAM_CLK_CNTL	0x03000000	0x2000000	RW	0x1090130	DDR SDRAM clock control	
DDR_INIT_ADDR	0x00000000	0x0	RW	0x1090148	DDR training initialization address	
DDR_INIT_EXT_ADDRESS	0x00000000	0x0	RW	0x109014c	DDR training initialization extended address	
TIMING_CFG_4	0x00220002	0x0	RW	0x1090160	DDR SDRAM timing configuration 4	
TIMING_CFG_5	0x04401400	0x0	RW	0x1090164	DDR SDRAM timing configuration 5	
TIMING_CFG_7	0x25500000	0x0	RW	0x109016c	DDR SDRAM timing configuration 7	
DDR_ZQ_CNTL	0x8a090705	0x0	RW	0x1090170	DDR ZQ calibration control	
DDR_WRLVL_CNTL	0xc675060a	0x0	RW	0x1090174	DDR write leveling control	
DDR_SR_CNTR	0x00000000	0x0	RW	0x109017c	DDR Self Refresh Counter	
DDR_SDRAM_RCW_1	0x00000000	0x0	RW	0x1090180	DDR Register Control Words 1	
DDR_SDRAM_RCW_2	0x00000000	0x0	RW	0x1090184	DDR Register Control Words 2	
DDR_WRLVL_CNTL_2	0x0b0c0e11	0x0	RW	0x1090190	DDR write leveling control 2	
DDR_WRLVL_CNTL_3	0x1214140f	0x0	RW	0x1090194	DDR write leveling control 3	
DDR_SDRAM_RCW_3	0x00000000	0x0	RW	0x10901a0	DDR Register Control Words 3	
DDR_SDRAM_RCW_4	0x00000000	0x0	RW	0x10901a4	DDR Register Control Words 4	
DDR_SDRAM_RCW_5	0x00000000	0x0	RW	0x10901a8	DDR Register Control Words 5	
DDR_SDRAM_RCW_6	0x00000000	0x0	RW	0x10901ac	DDR Register Control Words 6	
DDR_SDRAM_MODE_3	0x00010421	0x0	RW	0x1090200	DDR SDRAM mode configuration 3	
DDR_SDRAM_MODE_4	0x00080200	0x0	RW	0x1090204	DDR SDRAM mode configuration 4	
DDR_SDRAM_MODE_5	0x00010421	0x0	RW	0x1090208	DDR SDRAM mode configuration 5	
DDR_SDRAM_MODE_6	0x00080200	0x0	RW	0x109020c	DDR SDRAM mode configuration 6	
DDR_SDRAM_MODE_7	0x00010421	0x0	RW	0x1090210	DDR SDRAM mode configuration 7	
DDR_SDRAM_MODE_8	0x00080200	0x0	RW	0x1090214	DDR SDRAM mode configuration 8	
DDR_SDRAM_MODE_9	0x00000500	0x0	RW	0x1090220	DDR SDRAM mode configuration 9	
DDR_SDRAM_MODE_10	0x04400000	0x0	RW	0x1090224	DDR SDRAM mode configuration 10	
DDR_SDRAM_MODE_11	0x00000400	0x0	RW	0x1090228	DDR SDRAM mode configuration 11	
DDR_SDRAM_MODE_12	0x04400000	0x0	RW	0x109022c	DDR SDRAM mode configuration 12	
DDR_SDRAM_MODE_13	0x00000400	0x0	RW	0x1090230	DDR SDRAM mode configuration 13	
DDR_SDRAM_MODE_14	0x04400000	0x0	RW	0x1090234	DDR SDRAM mode configuration 14	
DDR_SDRAM_MODE_15	0x00000400	0x0	RW	0x1090238	DDR SDRAM mode configuration 15	
DDR_SDRAM_MODE_16	0x04400000	0x0	RW	0x109023c	DDR SDRAM mode configuration 16	
TIMING_CFG_8	0x03335900	0x0	RW	0x1090250	DDR SDRAM timing configuration 8	
DDR_SDRAM_CFG_3	0x00000000	0x0	RW	0x1090260	DDR SDRAM control configuration 3	
DDR_DQ_MAP0	0x32c57554	0x0	RW	0x1090400	DQ mapping register 0	
DDR_DQ_MAP1	0xd4bb0bd4	0x0	RW	0x1090404	DQ mapping register 1	
DDR_DQ_MAP2	0x2ec2f554	0x0	RW	0x1090408	DQ mapping register 2	
DDR_DQ_MAP3	0xd95d4001	0x0	RW	0x109040c	DQ mapping register 3	
DDRDSR_1	0x00008080	0x8080	R	0x1090b20	DDR Debug Status Register 1	
DDRDSR_2	0x80000000	0x80000000	RW	0x1090b24	DDR Debug Status Register 2	
DDRCDR_1	0x80080000	0x0	RW	0x1090b28	DDR Control Driver Register 1	
DDRCDR_2	0x000000c0	0x0	RW	0x1090b2c	DDR Control Driver Register 2	
DDR_IP_REV1	0x00020502	0x20502	R	0x1090bf8	DDR IP block revision 1	
DDR_IP_REV2	0x00000100	0x0	R	0x1090bfc	DDR IP block revision 2	
DDR_MTCR	0x00000000	0x0	RW	0x1090d00	DDR Memory Test Control Register	
DDR_MTP1	0x00000000	0x0	RW	0x1090d20	DDR Memory Test Pattern n Register	
DDR_MTP2	0x00000000	0x0	RW	0x1090d24	DDR Memory Test Pattern n Register	
DDR_MTP3	0x00000000	0x0	RW	0x1090d28	DDR Memory Test Pattern n Register	
DDR_MTP4	0x00000000	0x0	RW	0x1090d2c	DDR Memory Test Pattern n Register	
DDR_MTP5	0x00000000	0x0	RW	0x1090d30	DDR Memory Test Pattern n Register	
DDR_MTP6	0x00000000	0x0	RW	0x1090d34	DDR Memory Test Pattern n Register	
DDR_MTP7	0x00000000	0x0	RW	0x1090d38	DDR Memory Test Pattern n Register	
DDR_MTP8	0x00000000	0x0	RW	0x1090d3c	DDR Memory Test Pattern n Register	
DDR_MTP9	0x00000000	0x0	RW	0x1090d40	DDR Memory Test Pattern n Register	
DDR_MTP10	0x00000000	0x0	RW	0x1090d44	DDR Memory Test Pattern n Register	
DDR_MT_ST_EXT_ADDR	0x00000000	0x0	RW	0x1090d60	DDR Memory Test Start Extended Address	
DDR_MT_ST_ADDR	0x00000000	0x0	RW	0x1090d64	DDR Memory Test Start Address	
DDR_MT_END_EXT_ADDR	0x00000000	0x0	RW	0x1090d68	DDR Memory Test End Extended Address	
DDR_MT_END_ADDR	0x00000000	0x0	RW	0x1090d6c	DDR Memory Test End Address	
DATA_ERR_INJECT_HI	0x00000000	0x0	RW	0x1090e00	Memory data path error injection mask high	
DATA_ERR_INJECT_LO	0x00000000	0x0	RW	0x1090e04	Memory data path error injection mask low	
ECC_ERR_INJECT	0x00000000	0x0	RW	0x1090e08	Memory data path error injection mask ECC	
CAPTURE_DATA_HI	0x00000000	0x0	RW	0x1090e20	Memory data path read capture high	
CAPTURE_DATA_LO	0x00000000	0x0	RW	0x1090e24	Memory data path read capture low	
CAPTURE_ECC	0x00000000	0x0	RW	0x1090e28	Memory data path read capture ECC	
ERR_DETECT	0x00000000	0x0	RW	0x1090e40	Memory error detect	
ERR_DISABLE	0x00000000	0x0	RW	0x1090e44	Memory error disable	
ERR_INT_EN	0x00000000	0x0	RW	0x1090e48	Memory error interrupt enable	
CAPTURE_ATTRIBUTES	0x00000000	0x0	RW	0x1090e4c	Memory error attributes capture	
CAPTURE_ADDRESS	0x00000000	0x0	RW	0x1090e50	Memory error address capture	
CAPTURE_EXT_ADDRESS	0x00000000	0x0	RW	0x1090e54	Memory error extended address capture	
ERR_SBE	0x00000000	0x0	RW	0x1090e58	Single-Bit ECC memory error management	
	

 

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Contributor I

There are also a couple of undocumented registers used from CCSR DDR controller #1 space:

0x01080254: Cleared during memory controller set up
0x01080F04: Set to 0x00000400 when enabling the memory controller and then tested 0x00000002
0x01080F70: Set to 0x00000400 when enabling the memory controller and then cleared when waiting for memory controller start-up

What do these do?  Should they be documented?

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NXP TechSupport
NXP TechSupport

Attached is ZIP package with configuration files for the LS2088ARDB with 32 GB SDRAM.

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Contributor I

No joy.  I am still seeing "cannot read from address 0x80000000" in connection diagnostics.  Switch block#7 is 0x43.  That's the only deviation from the readme file.  The .py file that ufedor provided does not run as a target initialization script due to missing "cw_info" import.

These settings still look wrong.  Shouldn't CS0_BNDS and CS1_BNDS be set to 0x000007FF?  That is the value I see when probing Yocto. 

This is CCSR register space for memory controller #1, extracted while Yocto was running:

# B::Data.Dump_(0x1080000..0x01080FFF)_/LONG_/DIALOG_/COLumns_8
# ________________address|________0________4________8________C________0________4________8________C_0123456789ABCDEF0123456789ABCDEF
# MD:01080000|>000007FF 00000000 000007FF 00000000 00000000 00000000 00000000 00000000 ................................
# MD:01080020| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:01080040| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:01080060| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:01080080| A8050422 80000422 00000000 00000000 00000000 00000000 00000000 00000000 "..."...........................
# MD:010800A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:010800C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:010800E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:01080100| 01131100 91660018 DED8F045 00512154 E5004000 00401141 03010421 00080200 ......f.E...T!Q..@..A.@.!.......
# MD:01080120| 1600046B 1C70071C DEADBEEF 00000000 03000000 00000000 00000000 00000000 k.....p.........................
# MD:01080140| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:01080160| 00220002 04401400 00000000 25500000 8A090705 C675060A 00000000 00000000 .."...@.......P%......u.........
# MD:01080180| 00000000 00000000 00000000 00000000 0B0C0E11 1214140F 00000000 00000000 ................................
# MD:010801A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:010801C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:010801E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:01080200| 00010421 00080200 00010421 00080200 00010421 00080200 00000000 00000000 !.......!.......!...............
# MD:01080220| 00000500 04400000 00000400 04400000 00000400 04400000 00000400 04400000 ......@.......@.......@.......@.
# MD:01080240| 00000000 00000000 00000000 00000000 03335900 00000000 00000000 00000000 .................Y3.............
# MD:01080260| 00000000 00000000 00000000 00000000 0000FFFF 00000000 00000000 00000000 ................................
# MD:01080280| DDEEEEED EEEDEEED 22111112 11121112 11EE0001 00000000 00000000 00000000 ..........."....................
# MD:010802A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:010802C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
# MD:010802E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................

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NXP TechSupport
NXP TechSupport

According to the LS2088ARDB-PC BOM there are three DDR4 SDRAM UDIMM modules MTA18ASF1G72AZ-2G3B1 (8GB each).

So having CS0_BNDS and CS1_BNDS be set to 0x000003FF (16 GB ) is correct.

 

You wrote:

> Yocto running on the same set of boards

What exactly do you mean?

Which boards?

Please provide U-Boot log.

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Contributor I

U-Boot 2016.092.0+ga06b209 (Mar 30 2017 - 01:15:01 +0800)

SoC: LS2088AE Rev1.1 (0x87090011)
Clock Configuration:
CPU0(A72):1800 MHz CPU1(A72):1800 MHz CPU2(A72):1800 MHz
CPU3(A72):1800 MHz CPU4(A72):1800 MHz CPU5(A72):1800 MHz
CPU6(A72):1800 MHz CPU7(A72):1800 MHz
Bus: 700 MHz DDR: 1866.667 MT/s DP-DDR: 1600 MT/s
Reset Configuration Word (RCW):
00000000: 483038b8 48480048 00000000 00000000
00000010: 00000000 00000000 00a00000 00000000
00000020: 01001180 00002581 00000000 00000000
00000030: 00000c0b 00000000 00000000 00000000
00000040: 00000000 00000000 00000000 00000000
00000050: 00000000 00000000 00000000 00000000
00000060: 00000000 00000000 00027000 00000000
00000070: 412a0000 00000000
Model: Freescale Layerscape 2080a RDB Board
Board: LS2088AE Rev1.1-RDB, Board Arch: V1, Board version: F, boot from vBank: 0
FPGA: v1.22
SERDES1 Reference : Clock1 = 156.25MHz Clock2 = 156.25MHz
SERDES2 Reference : Clock1 = 100MHz Clock2 = 100MHz
I2C: ready
DRAM: Initializing DDR....using SPD
Detected UDIMM 18ADF2G72AZ-3G2E1
Detected UDIMM 18ADF2G72AZ-3G2E1
DP-DDR: Detected UDIMM 18ADF2G72AZ-3G2E1
38.5 GiB
DDR 30.5 GiB (DDR4, 64-bit, CL=13, ECC on)
DDR Controller Interleaving Mode: 256B
DDR Chip-Select Interleaving Mode: CS0+CS1
DP-DDR 8 GiB (DDR4, 32-bit, CL=11, ECC on)
DDR Chip-Select Interleaving Mode: CS0+CS1
SEC0: RNG instantiated
PPA Firmware: Version 0.2
Using SERDES1 Protocol: 42 (0x2a)
Using SERDES2 Protocol: 65 (0x41)
Flash: 128 MiB
NAND: 2048 MiB
MMC: FSL_SDHC: 0
EEPROM: NXID v1
In: serial
Out: serial
Err: serial
Debug Server FW: Bad FIT image format
VID: Core voltage after adjustment is at 1023 mV
SATA link 0 timeout.
AHCI 0001.0301 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
flags: 64bit ncq pm clo only pmp fbss pio slum part ccc apst
Found 0 device(s).

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Contributor I

I have more than one LS2088ARDB board.  The memory config cited above is typical.  The boards are 60 miles away in a locked room.  The attached picture shows a 16GB MTA18ADF2G72AZ-3G2.  It appears to be a dual-rank DIMM, but the picture is not clear enough that I can tell for sure.

800px-LS2088ARDB_SN201_DIMM.jpg

I will follow up with UBOOT console spew as time permits.

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NXP TechSupport
NXP TechSupport

You wrote:

> I cannot get memory to initialize, even to do connection diagnostics

Please explain corresponding steps and the results in detail.

Please consider that it is possible to use U-Boot "md" command to dump the DDR controller registers, compare the values with ones in the existing configuration file and modify it accordingly.

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