Hi,
I'm having trouble getting RCW sorted out to get both PCI slots on the LS1046ARDB to probe at gen3 speeds.
With the default 1133_5559 configuration from LSDK20.04 I get two cards to probe at gen2 speeds, and they work as expected:
PCIe0: pcie@3400000 Root Complex: no link
PCIe1: pcie@3500000 Root Complex: x1 gen2
PCIe2: pcie@3600000 Root Complex: x1 gen2
However, I haven't been able to find a configuration that sees two gen3 cards.
I've tried 1133_5506 and 1133_0506 without success. I've attached my current 1133_0506 RCW file, based on information from both the ls1046ardb 1133_5506 and ls1046aqds/RR_FNNQNPNP_1040_0506 configs.
With any configuration that I can seem to get booting I see just a single card:
PCIe0: pcie@3400000 disabled
PCIe1: pcie@3500000 Root Complex: x1 gen3
PCIe2: pcie@3600000 Root Complex: no link
Has anyone gotten both PCI slots working at gen3 speeds with LS1046ARDB?
Thanks,
/*
* LS1046ARDB RCW for SerDes Protocol 0x1133_0506
*
* 24G configuration -- 2 RGMII + two XFI + 2 SGMII + 2 PCIe
*
* Frequencies:
*
* Sys Clock: 100 MHz
* DDR_Refclock: 100 MHz
*
* Core -- 1600 MHz (Mul 16)
* Platform -- 600 MHz (Mul 6)
* DDR -- 2100 MT/s (Mul 21)
* FMan -- 700 MHz (CGA2 /2)
* XFI -- 156.25 MHz (10.3125G)
* SGMII -- 100 MHz (5G)
* PCIE -- 125 MHz (8G)
* eSDHC -- 1400 MHz (CGA2 /1)
*
* Hardware Accelerator Block Cluster Group A Mux Clock:
* FMan - HWA_CGA_M1_CLK_SEL = 6 - Async mode, CGA PLL 2 /2 is clock
* eSDHC, QSPI - HWA_CGA_M2_CLK_SEL = 1 - Async mode, CGA PLL 2 /1 is clock
*
* Serdes Lanes vs Slot information
* Serdes1 Lane 0 (D) - XFI9, AQR107 PHY
* Serdes1 Lane 1 (C) - XFI10, SFP cage
* Serdes1 Lane 2 (B) - SGMII5, SGMII1 port
* Serdes1 Lane 3 (A) - SGMII6, SGMII2 port
*
* Serdes2 Lane 0 (A) - Disabled (was: PCIe1 Gen3 x1, Slot 1, mPCIe)
* Serdes2 Lane 1 (B) - PCIe2 Gen3 x1, Slot 2
* Serdes2 Lane 2 (C) - Disabled
* Serdes2 Lane 3 (D) - PCIe3 Gen3 x1, Slot 3
*
* PLL mapping: 2211_1111
*
* Serdes 1:
* PLL mapping: 2211
*
* SRDS_PLL_REF_CLK_SEL_S1 : 0b'01
* SerDes 1, PLL1[160] : 0 - 100MHz for SGMII
* SerDes 1, PLL2[161] : 1 - 156.25MHz for XFI
* SRDS_PLL_PD_S1 : 0b'0
* SerDes 1, PLL1 : 0 - not power down
* SerDes 1, PLL2 : 0 - not power down
* HWA_CGA_M1_CLK_SEL[224-226] : 6 - Cluster Group A PLL 2 /2 to FMan
*
* Serdes 2:
* PLL mapping: 1111
* SRDS_PLL_REF_CLK_SEL_S2 : 0b'00
* SerDes 2, PLL1[162] : 0 - 100MHz for PCIe
* SerDes 2, PLL2[163] : 0 - Disabled
* SRDS_PLL_PD_S2 : 0b'10
* SerDes 2, PLL1 : 1 - power down
* SerDes 2, PLL2 : 0 - not power down
* SRDS_DIV_PEX_S2 : 0b'00
* 00 - train up to max rate of 8G
* 01 - train up to max rate of 5G
* 10 - train up to max rate of 2.5G
*
* DDR clock:
* DDR_REFCLK_SEL : 1 - DDRCLK pin provides the reference clock to the DDR PLL
*
*/
#include <ls1046a.rcwi>
SYS_PLL_RAT=6
MEM_PLL_RAT=21
CGA_PLL1_RAT=14
CGA_PLL2_RAT=14
SRDS_PRTCL_S1=4403
SRDS_PRTCL_S2=1286
SRDS_PLL_REF_CLK_SEL_S1=1
SRDS_PLL_REF_CLK_SEL_S2=0
/* SRDS_PLL_PD_S2=2 */
SRDS_DIV_PEX_S1=0
SRDS_DIV_PEX_S2=0
DDR_FDBK_MULT=2
DDR_REFCLK_SEL=1
PBI_src=6
IFC_MODE=64
HWA_CGA_M1_CLK_SEL=6
DRAM_LAT=1
SPI_EXT=1
UART_BASE=7
IFC_GRP_A_EXT=1
IFC_GRP_D_EXT=1
IFC_GRP_E1_EXT=1
IFC_GRP_F_EXT=1
IRQ_OUT=1
TVDD_VSEL=1
DVDD_VSEL=2
EVDD_VSEL=2
IIC2_EXT=1
SYSCLK_FREQ=600
HWA_CGA_M2_CLK_SEL=1
.pbi
write 0x570600, 0x00000000
write 0x570604, 0x10000000
.end
#include <cci_barrier_disable.rcw>
#include <usb_phy_freq.rcw>
#include <serdes_sata.rcw>
#include <pex_gen3_link.rcw>
#include <a009531.rcw>
.pbi
// Alt base register
write 0x570158, 0x00001000
.end
.pbi
// flush PBI data
write 0x6100c0, 0x000fffff
.end
