LS1046ARDB Clock Circuit

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LS1046ARDB Clock Circuit

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matthej
Contributor II
 

The LS1046ARDB  eval board uses a 6V49205 clock generator which produces a HCSL output, but the LS1046 input is LVDS. I have attached the section of the 6V49205 datasheet which describes the output clock:

 
matthej_2-1622645344468.png

 

 

The clock input is specified in this attached picture.

 
matthej_3-1622645455719.png

 

 

The eval board uses 50 ohm to ground termination on the output. I am having a hard time in seeing how this interface will work.

If you look at note 7 for the clock output it says the amplitude will be 1/2 of what is listed but the swing looks to be greater than the input can handle.

Output swing (max): 1150/2 - (-300/2) = 725mV, but the input says it can only handle a 600mV

Am I missing something here?

Thanks!

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ufedor
NXP TechSupport
NXP TechSupport

You also have to consider divider consisting of serial and ground resistors:

serial.jpgground.jpg

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ufedor
NXP TechSupport
NXP TechSupport

Which exactly LS1046A clock is in question?

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matthej
Contributor II

The DIFF_SYSCLK and DIFF_SYSCLK_B clock inputs

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ufedor
NXP TechSupport
NXP TechSupport

You also have to consider divider consisting of serial and ground resistors:

serial.jpgground.jpg