LS1046A-based board issue with DDR registers between TF-A (BL2 -> BL3 stage)

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LS1046A-based board issue with DDR registers between TF-A (BL2 -> BL3 stage)

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JRRandall
Contributor III

Greetings,

We have a LS1046A-based board we are trying to bring up, but it hangs right before BL33 (u-boot).  We have used QCVS to get the optimal values of DDR for our board.  From the LSDK literature, it appears the TF-A boot flow is “Boot ROM -> BL2 (DDR Init) -> BL31 ->U-boot”.  We have a Discrete DDR and we have made sure to enable CONFIG_STATIC_DDR.

When we attach the cwtap tool while in BL2, we can dump the DDR registers and see the following (desired values).

(gdb) reg_print DDR
Register                | Bit    | Value      | Reset      | Location   | RW | Description
Name                    | Range  | (hex)      | (hex)      | (hex)      |    |
------------------------------------------------------------------------------------------------------------------------
DDR_CS0_BNDS            |   0:31 | 0x000000ff | 0x00000000 | 0x01080000 | RW | Chip select memory bounds
DDR_CS1_BNDS            |   0:31 | 0x00000000 | 0x00000000 | 0x01080008 | RW | Chip select memory bounds
DDR_CS2_BNDS            |   0:31 | 0x00000000 | 0x00000000 | 0x01080010 | RW | Chip select memory bounds
DDR_CS3_BNDS            |   0:31 | 0x00000000 | 0x00000000 | 0x01080018 | RW | Chip select memory bounds
DDR_CS0_CONFIG          |   0:31 | 0x80440412 | 0x00000000 | 0x01080080 | RW | Chip select n configuration
DDR_CS1_CONFIG          |   0:31 | 0x00000000 | 0x00000000 | 0x01080084 | RW | Chip select n configuration
DDR_CS2_CONFIG          |   0:31 | 0x00000000 | 0x00000000 | 0x01080088 | RW | Chip select n configuration
DDR_CS3_CONFIG          |   0:31 | 0x00000000 | 0x00000000 | 0x0108008c | RW | Chip select n configuration
DDR_CS0_CONFIG_2        |   0:31 | 0x00000000 | 0x00000000 | 0x010800c0 | RW | Chip select n configuration 2
DDR_CS1_CONFIG_2        |   0:31 | 0x00000000 | 0x00000000 | 0x010800c4 | RW | Chip select n configuration 2
DDR_CS2_CONFIG_2        |   0:31 | 0x00000000 | 0x00000000 | 0x010800c8 | RW | Chip select n configuration 2
DDR_CS3_CONFIG_2        |   0:31 | 0x00000000 | 0x00000000 | 0x010800cc | RW | Chip select n configuration 2
DDR_TIMING_CFG_3        |   0:31 | 0x02101100 | 0x00000000 | 0x01080100 | RW | DDR SDRAM timing configuration 3
DDR_TIMING_CFG_0        |   0:31 | 0xd1770018 | 0x00110005 | 0x01080104 | RW | DDR SDRAM timing configuration 0
DDR_TIMING_CFG_1        |   0:31 | 0xf2fc9265 | 0x00000000 | 0x01080108 | RW | DDR SDRAM timing configuration 1
DDR_TIMING_CFG_2        |   0:31 | 0x00594197 | 0x00000000 | 0x0108010c | RW | DDR SDRAM timing configuration 2
DDR_SDRAM_CFG           |   0:31 | 0xe5000000 | 0x07000000 | 0x01080110 | RW | DDR SDRAM control configuration
DDR_SDRAM_CFG_2         |   0:31 | 0x00401140 | 0x00000000 | 0x01080114 | RW | DDR SDRAM control configuration 2
DDR_SDRAM_MODE          |   0:31 | 0x01010631 | 0x00000000 | 0x01080118 | RW | DDR SDRAM mode configuration
DDR_SDRAM_MODE_2        |   0:31 | 0x00100200 | 0x00000000 | 0x0108011c | RW | DDR SDRAM mode configuration 2
DDR_SDRAM_MD_CNTL       |   0:31 | 0x0600081f | 0x00000000 | 0x01080120 | RW | DDR SDRAM mode control
DDR_SDRAM_INTERVAL      |   0:31 | 0x0fff03ff | 0x00000000 | 0x01080124 | RW | DDR SDRAM interval configuration
DDR_DATA_INIT           |   0:31 | 0xdeadbeef | 0x00000000 | 0x01080128 | RW | DDR SDRAM data initialization
DDR_SDRAM_CLK_CNTL      |   0:31 | 0x01c00000 | 0x02000000 | 0x01080130 | RW | DDR SDRAM clock control
DDR_INIT_ADDR           |   0:31 | 0x00000000 | 0x00000000 | 0x01080148 | RW | DDR training initialization address
DDR_INIT_EXT_ADDRESS    |   0:31 | 0x00000000 | 0x00000000 | 0x0108014c | RW | DDR training initialization extended a...
DDR_TIMING_CFG_4        |   0:31 | 0x00220002 | 0x00000000 | 0x01080160 | RW | DDR SDRAM timing configuration 4
DDR_TIMING_CFG_5        |   0:31 | 0x05401400 | 0x00000000 | 0x01080164 | RW | DDR SDRAM timing configuration 5
DDR_TIMING_CFG_6        |   0:31 | 0x00000000 | 0x00000000 | 0x01080168 | RW | DDR SDRAM timing configuration 6
DDR_TIMING_CFG_7        |   0:31 | 0x26600000 | 0x00000000 | 0x0108016c | RW | DDR SDRAM timing configuration 7
DDR_ZQ_CNTL             |   0:31 | 0x8a090705 | 0x00000000 | 0x01080170 | RW | DDR ZQ calibration control
DDR_WRLVL_CNTL          |   0:31 | 0xc675f605 | 0x00000000 | 0x01080174 | RW | DDR write leveling control
DDR_SR_CNTR             |   0:31 | 0x00000000 | 0x00000000 | 0x0108017c | RW | DDR Self Refresh Counter
DDR_SDRAM_RCW_1         |   0:31 | 0x00000000 | 0x00000000 | 0x01080180 | RW | DDR Register Control Words 1
DDR_SDRAM_RCW_2         |   0:31 | 0x00000000 | 0x00000000 | 0x01080184 | RW | DDR Register Control Words 2
DDR_WRLVL_CNTL_2        |   0:31 | 0x05060605 | 0x00000000 | 0x01080190 | RW | DDR write leveling control 2
DDR_WRLVL_CNTL_3        |   0:31 | 0x06050505 | 0x00000000 | 0x01080194 | RW | DDR write leveling control 3
DDR_SDRAM_RCW_3         |   0:31 | 0x00000000 | 0x00000000 | 0x010801a0 | RW | DDR Register Control Words 3
DDR_SDRAM_RCW_4         |   0:31 | 0x00000000 | 0x00000000 | 0x010801a4 | RW | DDR Register Control Words 4
DDR_SDRAM_RCW_5         |   0:31 | 0x00000000 | 0x00000000 | 0x010801a8 | RW | DDR Register Control Words 5
DDR_SDRAM_RCW_6         |   0:31 | 0x00000000 | 0x00000000 | 0x010801ac | RW | DDR Register Control Words 6
DDR_SDRAM_MODE_3        |   0:31 | 0x00000000 | 0x00000000 | 0x01080200 | RW | DDR SDRAM mode configuration 3
DDR_SDRAM_MODE_4        |   0:31 | 0x00000000 | 0x00000000 | 0x01080204 | RW | DDR SDRAM mode configuration 4
DDR_SDRAM_MODE_5        |   0:31 | 0x00000000 | 0x00000000 | 0x01080208 | RW | DDR SDRAM mode configuration 5
DDR_SDRAM_MODE_6        |   0:31 | 0x00000000 | 0x00000000 | 0x0108020c | RW | DDR SDRAM mode configuration 6
DDR_SDRAM_MODE_7        |   0:31 | 0x00000000 | 0x00000000 | 0x01080210 | RW | DDR SDRAM mode configuration 7
DDR_SDRAM_MODE_8        |   0:31 | 0x00000000 | 0x00000000 | 0x01080214 | RW | DDR SDRAM mode configuration 8
DDR_SDRAM_MODE_9        |   0:31 | 0x00000500 | 0x00000000 | 0x01080220 | RW | DDR SDRAM mode configuration 9
DDR_SDRAM_MODE_10       |   0:31 | 0x08000000 | 0x00000000 | 0x01080224 | RW | DDR SDRAM mode configuration 10
DDR_SDRAM_MODE_11       |   0:31 | 0x00000000 | 0x00000000 | 0x01080228 | RW | DDR SDRAM mode configuration 11
DDR_SDRAM_MODE_12       |   0:31 | 0x00000000 | 0x00000000 | 0x0108022c | RW | DDR SDRAM mode configuration 12
DDR_SDRAM_MODE_13       |   0:31 | 0x00000000 | 0x00000000 | 0x01080230 | RW | DDR SDRAM mode configuration 13
DDR_SDRAM_MODE_14       |   0:31 | 0x00000000 | 0x00000000 | 0x01080234 | RW | DDR SDRAM mode configuration 14
DDR_SDRAM_MODE_15       |   0:31 | 0x00000000 | 0x00000000 | 0x01080238 | RW | DDR SDRAM mode configuration 15
DDR_SDRAM_MODE_16       |   0:31 | 0x00000000 | 0x00000000 | 0x0108023c | RW | DDR SDRAM mode configuration 16
DDR_TIMING_CFG_8        |   0:31 | 0x05446a00 | 0x00000000 | 0x01080250 | RW | DDR SDRAM timing configuration 8
DDR_SDRAM_CFG_3         |   0:31 | 0x00000000 | 0x00000000 | 0x01080260 | RW | DDR SDRAM control configuration 3
DDR_DESKEW_CNTL         |   0:31 | 0x00000000 | 0x00000000 | 0x010802a0 | RW | DDR Deskew Control
DDR_DQ_MAP0             |   0:31 | 0x475953a4 | 0x00000000 | 0x01080400 | RW | DQ mapping register 0
DDR_DQ_MAP1             |   0:31 | 0x2d2c55bc | 0x00000000 | 0x01080404 | RW | DQ mapping register 1
DDR_DQ_MAP2             |   0:31 | 0x0f2bd460 | 0x00000000 | 0x01080408 | RW | DQ mapping register 2
DDR_DQ_MAP3             |   0:31 | 0x90ba8000 | 0x00000000 | 0x0108040c | RW | DQ mapping register 3
DDR_DDRDSR_1            |   0:31 | 0x00008080 | 0x00000000 | 0x01080b20 | R  | DDR Debug Status Register 1
DDR_DDRDSR_2            |   0:31 | 0x80000000 | 0x00000000 | 0x01080b24 | RW | DDR Debug Status Register 2
DDR_DDRCDR_1            |   0:31 | 0x80080000 | 0x00008080 | 0x01080b28 | RW | DDR Control Driver Register 1
DDR_DDRCDR_2            |   0:31 | 0x0000a180 | 0x08000000 | 0x01080b2c | RW | DDR Control Driver Register 2
DDR_IP_REV1             |   0:31 | 0x00020502 | 0x00000000 | 0x01080bf8 | R  | DDR IP block revision 1
DDR_IP_REV2             |   0:31 | 0x00000100 | 0x00000000 | 0x01080bfc | R  | DDR IP block revision 2
DDR_MTCR                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d00 | RW | DDR Memory Test Control Register
DDR_MTP1                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d20 | RW | DDR Memory Test Pattern n Register
DDR_MTP2                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d24 | RW | DDR Memory Test Pattern n Register
DDR_MTP3                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d28 | RW | DDR Memory Test Pattern n Register
DDR_MTP4                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d2c | RW | DDR Memory Test Pattern n Register
DDR_MTP5                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d30 | RW | DDR Memory Test Pattern n Register
DDR_MTP6                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d34 | RW | DDR Memory Test Pattern n Register
DDR_MTP7                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d38 | RW | DDR Memory Test Pattern n Register
DDR_MTP8                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d3c | RW | DDR Memory Test Pattern n Register
DDR_MTP9                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d40 | RW | DDR Memory Test Pattern n Register
DDR_MTP10               |   0:31 | 0x00000000 | 0x00000000 | 0x01080d44 | RW | DDR Memory Test Pattern n Register
DDR_MT_ST_EXT_ADDR      |   0:31 | 0x00000000 | 0x00000000 | 0x01080d60 | RW | DDR Memory Test Start Extended Address
DDR_MT_ST_ADDR          |   0:31 | 0x00000000 | 0x00000000 | 0x01080d64 | RW | DDR Memory Test Start Address
DDR_MT_END_EXT_ADDR     |   0:31 | 0x00000000 | 0x00000000 | 0x01080d68 | RW | DDR Memory Test End Extended Address
DDR_MT_END_ADDR         |   0:31 | 0x00000000 | 0x00000000 | 0x01080d6c | RW | DDR Memory Test End Address
DDR_DATA_ERR_INJECT_HI  |   0:31 | 0x00000000 | 0x00000000 | 0x01080e00 | RW | Memory data path error injection mask ...
DDR_DATA_ERR_INJECT_LO  |   0:31 | 0x00000000 | 0x00000000 | 0x01080e04 | RW | Memory data path error injection mask low
DDR_ECC_ERR_INJECT      |   0:31 | 0x00000000 | 0x00000000 | 0x01080e08 | RW | Memory data path error injection mask ECC
DDR_CAPTURE_DATA_HI     |   0:31 | 0x00000000 | 0x00000000 | 0x01080e20 | RW | Memory data path read capture high
DDR_CAPTURE_DATA_LO     |   0:31 | 0x00000000 | 0x00000000 | 0x01080e24 | RW | Memory data path read capture low
DDR_CAPTURE_ECC         |   0:31 | 0x00000000 | 0x00000000 | 0x01080e28 | RW | Memory data path read capture ECC
DDR_ERR_DETECT          |   0:31 | 0x00000000 | 0x00000000 | 0x01080e40 | RW | Memory error detect
DDR_ERR_DISABLE         |   0:31 | 0x00000000 | 0x00000000 | 0x01080e44 | RW | Memory error disable
DDR_ERR_INT_EN          |   0:31 | 0x00000000 | 0x00000000 | 0x01080e48 | RW | Memory error interrupt enable
DDR_CAPTURE_ATTRIBUTES  |   0:31 | 0x00000000 | 0x00000000 | 0x01080e4c | RW | Memory error attributes capture
DDR_CAPTURE_ADDRESS     |   0:31 | 0x00000000 | 0x00000000 | 0x01080e50 | RW | Memory error address capture
DDR_CAPTURE_EXT_ADDRESS |   0:31 | 0x00000000 | 0x00000000 | 0x01080e54 | RW | Memory error extended address capture
DDR_ERR_SBE             |   0:31 | 0x00000000 | 0x00000000 | 0x01080e58 | RW | Single-Bit ECC memory error management

When we attach the cwtap tool while in BL3, the DDR registers have been cleared to 0 by something in BL3 stage (maybe u-boot)?

(gdb) reg_print DDR
Register                | Bit    | Value      | Reset      | Location   | RW | Description
Name                    | Range  | (hex)      | (hex)      | (hex)      |    |
------------------------------------------------------------------------------------------------------------------------
DDR_CS0_BNDS            |   0:31 | 0x00000000 | 0x00000000 | 0x01080000 | RW | Chip select memory bounds
DDR_CS1_BNDS            |   0:31 | 0x00000000 | 0x00000000 | 0x01080008 | RW | Chip select memory bounds
DDR_CS2_BNDS            |   0:31 | 0x00000000 | 0x00000000 | 0x01080010 | RW | Chip select memory bounds
DDR_CS3_BNDS            |   0:31 | 0x00000000 | 0x00000000 | 0x01080018 | RW | Chip select memory bounds
DDR_CS0_CONFIG          |   0:31 | 0x00000000 | 0x00000000 | 0x01080080 | RW | Chip select n configuration
DDR_CS1_CONFIG          |   0:31 | 0x00000000 | 0x00000000 | 0x01080084 | RW | Chip select n configuration
DDR_CS2_CONFIG          |   0:31 | 0x00000000 | 0x00000000 | 0x01080088 | RW | Chip select n configuration
DDR_CS3_CONFIG          |   0:31 | 0x00000000 | 0x00000000 | 0x0108008c | RW | Chip select n configuration
DDR_CS0_CONFIG_2        |   0:31 | 0x00000000 | 0x00000000 | 0x010800c0 | RW | Chip select n configuration 2
DDR_CS1_CONFIG_2        |   0:31 | 0x00000000 | 0x00000000 | 0x010800c4 | RW | Chip select n configuration 2
DDR_CS2_CONFIG_2        |   0:31 | 0x00000000 | 0x00000000 | 0x010800c8 | RW | Chip select n configuration 2
DDR_CS3_CONFIG_2        |   0:31 | 0x00000000 | 0x00000000 | 0x010800cc | RW | Chip select n configuration 2
DDR_TIMING_CFG_3        |   0:31 | 0x00000000 | 0x00000000 | 0x01080100 | RW | DDR SDRAM timing configuration 3
DDR_TIMING_CFG_0        |   0:31 | 0x00110005 | 0x00110005 | 0x01080104 | RW | DDR SDRAM timing configuration 0
DDR_TIMING_CFG_1        |   0:31 | 0x00000000 | 0x00000000 | 0x01080108 | RW | DDR SDRAM timing configuration 1
DDR_TIMING_CFG_2        |   0:31 | 0x00000000 | 0x00000000 | 0x0108010c | RW | DDR SDRAM timing configuration 2
DDR_SDRAM_CFG           |   0:31 | 0x07000000 | 0x07000000 | 0x01080110 | RW | DDR SDRAM control configuration
DDR_SDRAM_CFG_2         |   0:31 | 0x00000000 | 0x00000000 | 0x01080114 | RW | DDR SDRAM control configuration 2
DDR_SDRAM_MODE          |   0:31 | 0x00000000 | 0x00000000 | 0x01080118 | RW | DDR SDRAM mode configuration
DDR_SDRAM_MODE_2        |   0:31 | 0x00000000 | 0x00000000 | 0x0108011c | RW | DDR SDRAM mode configuration 2
DDR_SDRAM_MD_CNTL       |   0:31 | 0x00000000 | 0x00000000 | 0x01080120 | RW | DDR SDRAM mode control
DDR_SDRAM_INTERVAL      |   0:31 | 0x00000000 | 0x00000000 | 0x01080124 | RW | DDR SDRAM interval configuration
DDR_DATA_INIT           |   0:31 | 0x00000000 | 0x00000000 | 0x01080128 | RW | DDR SDRAM data initialization
DDR_SDRAM_CLK_CNTL      |   0:31 | 0x02000000 | 0x02000000 | 0x01080130 | RW | DDR SDRAM clock control
DDR_INIT_ADDR           |   0:31 | 0x00000000 | 0x00000000 | 0x01080148 | RW | DDR training initialization address
DDR_INIT_EXT_ADDRESS    |   0:31 | 0x00000000 | 0x00000000 | 0x0108014c | RW | DDR training initialization extended a...
DDR_TIMING_CFG_4        |   0:31 | 0x00000000 | 0x00000000 | 0x01080160 | RW | DDR SDRAM timing configuration 4
DDR_TIMING_CFG_5        |   0:31 | 0x00000000 | 0x00000000 | 0x01080164 | RW | DDR SDRAM timing configuration 5
DDR_TIMING_CFG_6        |   0:31 | 0x00000000 | 0x00000000 | 0x01080168 | RW | DDR SDRAM timing configuration 6
DDR_TIMING_CFG_7        |   0:31 | 0x00000000 | 0x00000000 | 0x0108016c | RW | DDR SDRAM timing configuration 7
DDR_ZQ_CNTL             |   0:31 | 0x00000000 | 0x00000000 | 0x01080170 | RW | DDR ZQ calibration control
DDR_WRLVL_CNTL          |   0:31 | 0x00000000 | 0x00000000 | 0x01080174 | RW | DDR write leveling control
DDR_SR_CNTR             |   0:31 | 0x00000000 | 0x00000000 | 0x0108017c | RW | DDR Self Refresh Counter
DDR_SDRAM_RCW_1         |   0:31 | 0x00000000 | 0x00000000 | 0x01080180 | RW | DDR Register Control Words 1
DDR_SDRAM_RCW_2         |   0:31 | 0x00000000 | 0x00000000 | 0x01080184 | RW | DDR Register Control Words 2
DDR_WRLVL_CNTL_2        |   0:31 | 0x00000000 | 0x00000000 | 0x01080190 | RW | DDR write leveling control 2
DDR_WRLVL_CNTL_3        |   0:31 | 0x00000000 | 0x00000000 | 0x01080194 | RW | DDR write leveling control 3
DDR_SDRAM_RCW_3         |   0:31 | 0x00000000 | 0x00000000 | 0x010801a0 | RW | DDR Register Control Words 3
DDR_SDRAM_RCW_4         |   0:31 | 0x00000000 | 0x00000000 | 0x010801a4 | RW | DDR Register Control Words 4
DDR_SDRAM_RCW_5         |   0:31 | 0x00000000 | 0x00000000 | 0x010801a8 | RW | DDR Register Control Words 5
DDR_SDRAM_RCW_6         |   0:31 | 0x00000000 | 0x00000000 | 0x010801ac | RW | DDR Register Control Words 6
DDR_SDRAM_MODE_3        |   0:31 | 0x00000000 | 0x00000000 | 0x01080200 | RW | DDR SDRAM mode configuration 3
DDR_SDRAM_MODE_4        |   0:31 | 0x00000000 | 0x00000000 | 0x01080204 | RW | DDR SDRAM mode configuration 4
DDR_SDRAM_MODE_5        |   0:31 | 0x00000000 | 0x00000000 | 0x01080208 | RW | DDR SDRAM mode configuration 5
DDR_SDRAM_MODE_6        |   0:31 | 0x00000000 | 0x00000000 | 0x0108020c | RW | DDR SDRAM mode configuration 6
DDR_SDRAM_MODE_7        |   0:31 | 0x00000000 | 0x00000000 | 0x01080210 | RW | DDR SDRAM mode configuration 7
DDR_SDRAM_MODE_8        |   0:31 | 0x00000000 | 0x00000000 | 0x01080214 | RW | DDR SDRAM mode configuration 8
DDR_SDRAM_MODE_9        |   0:31 | 0x00000000 | 0x00000000 | 0x01080220 | RW | DDR SDRAM mode configuration 9
DDR_SDRAM_MODE_10       |   0:31 | 0x00000000 | 0x00000000 | 0x01080224 | RW | DDR SDRAM mode configuration 10
DDR_SDRAM_MODE_11       |   0:31 | 0x00000000 | 0x00000000 | 0x01080228 | RW | DDR SDRAM mode configuration 11
DDR_SDRAM_MODE_12       |   0:31 | 0x00000000 | 0x00000000 | 0x0108022c | RW | DDR SDRAM mode configuration 12
DDR_SDRAM_MODE_13       |   0:31 | 0x00000000 | 0x00000000 | 0x01080230 | RW | DDR SDRAM mode configuration 13
DDR_SDRAM_MODE_14       |   0:31 | 0x00000000 | 0x00000000 | 0x01080234 | RW | DDR SDRAM mode configuration 14
DDR_SDRAM_MODE_15       |   0:31 | 0x00000000 | 0x00000000 | 0x01080238 | RW | DDR SDRAM mode configuration 15
DDR_SDRAM_MODE_16       |   0:31 | 0x00000000 | 0x00000000 | 0x0108023c | RW | DDR SDRAM mode configuration 16
DDR_TIMING_CFG_8        |   0:31 | 0x00000000 | 0x00000000 | 0x01080250 | RW | DDR SDRAM timing configuration 8
DDR_SDRAM_CFG_3         |   0:31 | 0x00000000 | 0x00000000 | 0x01080260 | RW | DDR SDRAM control configuration 3
DDR_DESKEW_CNTL         |   0:31 | 0x00000000 | 0x00000000 | 0x010802a0 | RW | DDR Deskew Control
DDR_DQ_MAP0             |   0:31 | 0x00000000 | 0x00000000 | 0x01080400 | RW | DQ mapping register 0
DDR_DQ_MAP1             |   0:31 | 0x00000000 | 0x00000000 | 0x01080404 | RW | DQ mapping register 1
DDR_DQ_MAP2             |   0:31 | 0x00000000 | 0x00000000 | 0x01080408 | RW | DQ mapping register 2
DDR_DQ_MAP3             |   0:31 | 0x00000000 | 0x00000000 | 0x0108040c | RW | DQ mapping register 3
DDR_DDRDSR_1            |   0:31 | 0x00008080 | 0x00000000 | 0x01080b20 | R  | DDR Debug Status Register 1
DDR_DDRDSR_2            |   0:31 | 0x80000000 | 0x00000000 | 0x01080b24 | RW | DDR Debug Status Register 2
DDR_DDRCDR_1            |   0:31 | 0x00000000 | 0x00008080 | 0x01080b28 | RW | DDR Control Driver Register 1
DDR_DDRCDR_2            |   0:31 | 0x00000000 | 0x08000000 | 0x01080b2c | RW | DDR Control Driver Register 2
DDR_IP_REV1             |   0:31 | 0x00020502 | 0x00000000 | 0x01080bf8 | R  | DDR IP block revision 1
DDR_IP_REV2             |   0:31 | 0x00000100 | 0x00000000 | 0x01080bfc | R  | DDR IP block revision 2
DDR_MTCR                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d00 | RW | DDR Memory Test Control Register
DDR_MTP1                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d20 | RW | DDR Memory Test Pattern n Register
DDR_MTP2                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d24 | RW | DDR Memory Test Pattern n Register
DDR_MTP3                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d28 | RW | DDR Memory Test Pattern n Register
DDR_MTP4                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d2c | RW | DDR Memory Test Pattern n Register
DDR_MTP5                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d30 | RW | DDR Memory Test Pattern n Register
DDR_MTP6                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d34 | RW | DDR Memory Test Pattern n Register
DDR_MTP7                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d38 | RW | DDR Memory Test Pattern n Register
DDR_MTP8                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d3c | RW | DDR Memory Test Pattern n Register
DDR_MTP9                |   0:31 | 0x00000000 | 0x00000000 | 0x01080d40 | RW | DDR Memory Test Pattern n Register
DDR_MTP10               |   0:31 | 0x00000000 | 0x00000000 | 0x01080d44 | RW | DDR Memory Test Pattern n Register
DDR_MT_ST_EXT_ADDR      |   0:31 | 0x00000000 | 0x00000000 | 0x01080d60 | RW | DDR Memory Test Start Extended Address
DDR_MT_ST_ADDR          |   0:31 | 0x00000000 | 0x00000000 | 0x01080d64 | RW | DDR Memory Test Start Address
DDR_MT_END_EXT_ADDR     |   0:31 | 0x00000000 | 0x00000000 | 0x01080d68 | RW | DDR Memory Test End Extended Address
DDR_MT_END_ADDR         |   0:31 | 0x00000000 | 0x00000000 | 0x01080d6c | RW | DDR Memory Test End Address
DDR_DATA_ERR_INJECT_HI  |   0:31 | 0x00000000 | 0x00000000 | 0x01080e00 | RW | Memory data path error injection mask ...
DDR_DATA_ERR_INJECT_LO  |   0:31 | 0x00000000 | 0x00000000 | 0x01080e04 | RW | Memory data path error injection mask low
DDR_ECC_ERR_INJECT      |   0:31 | 0x00000000 | 0x00000000 | 0x01080e08 | RW | Memory data path error injection mask ECC
DDR_CAPTURE_DATA_HI     |   0:31 | 0x00000000 | 0x00000000 | 0x01080e20 | RW | Memory data path read capture high
DDR_CAPTURE_DATA_LO     |   0:31 | 0x00000000 | 0x00000000 | 0x01080e24 | RW | Memory data path read capture low
DDR_CAPTURE_ECC         |   0:31 | 0x00000000 | 0x00000000 | 0x01080e28 | RW | Memory data path read capture ECC
DDR_ERR_DETECT          |   0:31 | 0x00000000 | 0x00000000 | 0x01080e40 | RW | Memory error detect
DDR_ERR_DISABLE         |   0:31 | 0x00000000 | 0x00000000 | 0x01080e44 | RW | Memory error disable
DDR_ERR_INT_EN          |   0:31 | 0x00000000 | 0x00000000 | 0x01080e48 | RW | Memory error interrupt enable
DDR_CAPTURE_ATTRIBUTES  |   0:31 | 0x00000000 | 0x00000000 | 0x01080e4c | RW | Memory error attributes capture
DDR_CAPTURE_ADDRESS     |   0:31 | 0x00000000 | 0x00000000 | 0x01080e50 | RW | Memory error address capture
DDR_CAPTURE_EXT_ADDRESS |   0:31 | 0x00000000 | 0x00000000 | 0x01080e54 | RW | Memory error extended address capture
DDR_ERR_SBE             |   0:31 | 0x00000000 | 0x00000000 | 0x01080e58 | RW | Single-Bit ECC memory error management

We were under the impression that DDR initialization is done entirely within BL2.  This looks to be true and the values for our board DDR registers appear to be getting correctly set.  What’s troubling is that further down the boot chain in BL3 they are getting overwritten somehow.  Does the u-boot image need to have the correct DDR values if BL2 already sets them?

 

CodeWarrior QCVS generated source (and our current understanding of what they are)

InitDdrRegisters_1.c – For bare metal projects (we’re not using)

ddrTfa_1.c – For ARM Trusted Firmware (we are using with CONFIG_STATIC_DDR set)

uboot_ddr1.c – For u-boot (Is this needed independent of values being set in AT-F BL2??)

ddrCtrl_1.py – For testing DDR values with python init scripts and cwtap independent of build images

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JRRandall
Contributor III

We still haven't gotten this working, but we confirmed that cwtap has to reset the board to connect when we are in this state, which is why the DDR registers were in reset.  Truth be told we don't know what those register values are when the boot process gets hung up, because we have no way to connect up though cwtap at that point.

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ufedor
NXP Employee
NXP Employee

Is it possible to connect CodeWarrior in BL2?

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JRRandall
Contributor III

Yes when we are in BL2 we can connect cwtap and all looks good, the DDR registers are set to the values we determined from QCVS validation.  Something goes wrong in the jump to BL3.

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ufedor
NXP Employee
NXP Employee

> Something goes wrong in the jump to BL3.

Definitely this is not connected to the DDR controller.

Please try to debug the BL31.

Refer to the Layerscape Software Development Kit User Guide, 5.2 TF-A, TF-A boot flow.

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JRRandall
Contributor III

https://www.nxp.com/docs/en/user-guide/LSDKUG_Rev21.08.pdf  page 208

We are testing our custom LS1046A board and we keep doing back and forth between static DDR initialization.  It appears the LS1046A FRWY board we have is using dynamic DDR init by default?

I beleive the LS1046A SoC uses Discrete DDR, not a DIMM.  Can you confirm?  If so, it would appear that we want to:

Define macro “CONFIG_STATIC_DDR” in plat/nxp/<soc>/<board>/plafform_def.h to enable discrete DDR timings. Define board_static_ddr() function and structure ddr_cfg_regs in file ddr_init.c.

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ufedor
NXP Employee
NXP Employee

> I beleive the LS1046A SoC uses Discrete DDR, not a DIMM. Can you confirm?

The LS1046A SoC is just a processor itself - i.e. DDR SDRAM initialization have to be implemented in accordance with specific board design. If this specific design does not have SPD EEPROM containing the DDR SDRAM parameters, then described static DDR approach has to be used.

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ufedor
NXP Employee
NXP Employee

> We were under the impression that DDR initialization is done entirely within BL2.

Correct.

> in BL3 they are getting overwritten somehow.

The registers values correspond to reset state.

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JRRandall
Contributor III

Thanks for the quick response.  We're still seeing this behavior.  Does the u-boot image from the LSDK try to re-initialize the DDR?  I'm just trying to figure out how the SDRAM could go into reset unless something in BL3 stage is doing it.  

Worth mentioning that in our board, we have GPIO1[27] tied to DDR reset line.  It needs to be driven logical high (enabled) for DDR to come out of reset.  We do this using PBI commands in the PBL, and we can see in BL2 stage that the DDR is indeed out of reset and looking good.  Here are the PBI commands to enable GPIO1 for reference.

//===========================================================================
// set GPIO1[27] output high to take SDRAM out of reset
//===========================================================================
.pbi
write 0x570158, 0x00000200 // set SCFG_ALTCBAR=0x02000000 Big-Endian
flush
awrite 0x300000, 0x00000010 // GPDIR set GPIO1[27] direction to output
awrite 0x300008, 0x00000010 // GPDAT write data '1' (latched) to GPIO1[27]
.end
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ufedor
NXP Employee
NXP Employee

> Does the u-boot image from the LSDK try to re-initialize the DDR?

No.

> we have GPIO1[27] tied to DDR reset line.

This is not a recommended approach - refer to the AN5097 - Hardware and Layout Design Considerations for DDR4 SDRAM, Appendix B DRAM reset signal considerations.

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JRRandall
Contributor III

Thanks ufedor.  Not recommended but does this mean it won't work, i.e. we need a hardware mod?  Can you confirm if we need to put our DDR init values into u-boot i.e. uboot_ddr1.c source file that is generated from CodeWarrior QCVS or not, since we do see them getting set properly in BL2?

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ufedor
NXP Employee
NXP Employee

> does this mean it won't work, i.e. we need a hardware mod?

It could work, but hardware rework is recommended.

> we need to put our DDR init values into u-boot

Normally DDR controller initialization is performed only once in the BL2 - refer to the Layerscape Software Development Kit User Guide, Rev. 21.08, 5.2 TF-A, TF-A boot flow and 5.2.1.1 TF-A DDR Driver.