LS1046A DDR4 interface : VTT island and ECC doubts

[almudena_martin]

Hello,

I'm developing a board with LS1046A. I would like to use LS1046A DDR controller using x72 data bus: x64-bit data and x8-bit ECC. As a guide, I've seen the scheme of DDR4 in FRWYLS1046A-PA, so 4 DDR4 devices are used for data and one DDR4 device is used for ECC.

In our case, we are considering the use of DDR4 MT40A256M16LY-062 IT from Micron.

Regarding the design of FRWYLS1046A-PA and the use of MT40A256M16LY-062, I have certain doubts after reading AN5097 application note:

1) Item no. 8 and 9: in the VTT island it is recommended the use of one low ESL capacitor for each group of four termination resistors,  at least one 4.7uF cap and a bulk capacitor (47 - 220 uF) at each end of the VTT island.

However, in FRWYLS1046A-PA I only see two capacitors of 10 uF connected to DDR_VTT (VTT Power supply).  Additionally, there is a capacitor network used to decouple DDR_VTT( VTT Power supply) from GVDD (LS1046A DDR controller and DDR4 VDD power supplies). (Figure below)

So, which is the best way for decoupling the VTT island? Only acccording to AN5097 recommendations or including both methods?

Is it necessary to decouple DDR_VTT from GVDD? I don't find anything about this in NXP or Micron datasheets.

2)  Item no. 60:  it is stated to pull-up the eight unused DQ pins when 16-bit DRAM is used for ECC. On the other hand, TN4041 application note from Micron recommends to leave those pins unconnected. This last case is implemented in FRWYLS1046A-PA.  Are both type of connections valid? Which is the best solution?

Thank you in advance for your help.

[almudena_martin]

As I progress in our design, new doubts about DDR4 appears. This is not related with my previous question, but I need clarification about one issue:

LS1046 DDR Controller provides a clock signal DDRCLK (pin J20) . According to LS1046ARM, this signal is the reference clock to the DDR PLL and the configuration of the DDR PLL is done with Clocking_PLLDGSR  register (DDR PLL general status register).  In this register, it is necessary to set KILL bit = 0 to enable PLL performance and configure CFG field to fix the PLL multiplier where CFG field reflects the values programmed in RCW[MEM_PLL_RAT].

But according to Table 4-14 of LS1046ARM, MEM_PLL_RAT of RCW register configures the DDR PLL : SYSCLK ratio.

I understand that DDRCLK and SYSCLK are different clock signals. So , is DDR PLL obtained from DDRCLK or from SYSCLK?

Thank you in advance

[ufedor]

1) Method described in the AN5097 is preferable.

2) Both variants are possible.

[Urmila_123]

Hi ,

Could you please tell me, Is the below VTT termination(LS1043ARDB) abiding to AN5097? 

Thanks & Regards

Urmila P

[almudena_martin]

Thank you very much for your response ufedor.

As per your response, it is better to decouple VTT according to AN5097 application note. Regarding the recomentation of the use of one low ESL capacitor for each group of four termination resistors,  which value of capacitor is better to use? Or is it better to include two caps for each x4 resistor array (For example: 100nF and 10 nF per group)?

Regarding termination of ECC DDR4, if unused DQ pins are left unconnected, would DDR4 device suffer from integrity issues?

Thank you in advance.

[ufedor]

 100nF and 1uF per group.

> would DDR4 device suffer from integrity issues?

You wrote:

>> On the other hand, TN4041 application note from Micron recommends to leave those pins unconnected.

[almudena_martin]

Thank you very much for all your help.