LS1043A and LS1046A - SerDes REF_CLK

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LS1043A and LS1046A - SerDes REF_CLK

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juergene
Contributor III

Hello community,

i am working on a design with the LS1043A/46A processor. This processors should be exchangeable at one PCB-Design.

Is it needed to use all 4 SDx_REF_CLKx_P/N as input at the LS1046A or can i use the 2 SD1_REF_CLKx_P/N which the LS1043A provide. 

Are the 4 SDx_REF_CLKx_P/N depend on anything while using all 8 SerDes-Lanes ?

For Example:

SD1_REF_CLK1_P/N is needed for Lane A-B (SerDes1) and SD1_REF_CLK2_P/N is needed for Lane C-D (SerDes1).

Or can i switch the REF_CLK ?

Thanks,

Best regards,

Juergen

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ufedor
NXP TechSupport
NXP TechSupport

Note 2 and XFI clocking from PLL1 is incorrect in the Table 30-5.

Correct mapping is:

Lane       Interface      PLL-Mapping

D            XFI               2 
C            XFI               2 

B            SGMII           1 

A            SGMII           1

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juergene
Contributor III

Hi ufedor,

thanks for answering. Don't mind the question above, i had some wrong thoughts. I figured it out.

But i had another question:

This follow SerDes1 options shows the PLL-Mapping 2221 (XFI,XFI,SGMII,SGMII)

pastedImage_1.png

But the following note 2 says XFI can only be sourced from SerDes PLL1.

pastedImage_2.png

How can i understand that ?

Thanks,

Best regards,

Juergen

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ufedor
NXP TechSupport
NXP TechSupport

There is a typo in the note location marked yellow - correct is SerDes PLL2.

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juergene
Contributor III

But table 30-5 says that XFI can only sourced from PLL1 (also note 2)

pastedImage_1.png

In table 30-1 the order of PLL assignment is wrong?

For Example RCW: 0x1133

Lane       Interface      PLL-Mapping

D            XFI               2 
C            XFI               2 

B            SGMII           1 

A            SGMII           1

The right order should be:

Lane       Interface      PLL-Mapping

D            XFI               1 
C            XFI               1 

B            SGMII           2 

A            SGMII           2

Is this correct, because i can't find the typo.

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ufedor
NXP TechSupport
NXP TechSupport

Note 2 and XFI clocking from PLL1 is incorrect in the Table 30-5.

Correct mapping is:

Lane       Interface      PLL-Mapping

D            XFI               2 
C            XFI               2 

B            SGMII           1 

A            SGMII           1

View solution in original post

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juergene
Contributor III

Could anyone help me ?

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ufedor
NXP TechSupport
NXP TechSupport

PLLs used by specific protocols are shown in the processor's Reference Manuals:

LS1043A - Figure 32-1. Supported SerDes options, coulumn "PLL Napping"

LS1046A - Table 30-1. Supported SerDes1 options, column "PCIe Gen1/2 PLL Mapping"

The question is not clear because LS1043A has one SerDes, while LS1046A - two.

Please create a Technical Case so it will be possible to provide additional information concerning common board design:

https://community.freescale.com/thread/381898 

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