LS1043A DDR4 Simulation details

[logeshs]

Hi,

In LS1043A, We are simulating LS1043A for DDR4, To setup the Timing Model we need tDDKHDS/tDDKLDS and tDDKHDS/tDDKLDX these details which is missing from Datasheet in DDR4 Timing Diagram, Kindly request you to share me those details as soon as possible.

Thanks.

[Bulat]

The LS1043A has two main parameters for reads:
1) what you call "Data EYE Height" is defined by Vilac and Vihac, see table 33 of the datasheet;
2) data valid window should be minimum 2 x tCISKEW, see table 34 of the datasheet. Data valid window means time when all DQ signals of a byte lane are valid (item 1 above is met) and stable.

If these are met, reads will be successful.

Regards,
Bulat

[logeshs]

We also request you to share me 

1. Read Data Eye Mask,

2. Read Data Pulse Width,

3. Read Data EYE Height,

4. Read Slew rate,

5. Pulse width Uncertainity,

Kindly provide these values for performing DDR4 Simulation in HyperLynx. These details are not available in processor datasheet and Reference Manaual.