Hi NXP,
we plan to use three DDR4 256M x 16 (Micron MT40A256M16) in our system with LS1043. One of the DDR4 will be for ECC.
1) These DDR4 has an input called UDM and LDM. On the LS1021A-IOT evaluation board, only LDM on the ECC DDR4 is connected, UDM seems to be left open. Can this also be done on LS1043?
2) On the LS1021-IOT evaluation board, ODT1 from LS1021 is connected to NC on the DDR3 (pin J1). We do not have this pin on the DDR4. Should ODT1 on LS1043 be left open or terminated?
3) Also on LS1021-IOT evaluation board, CKE1 is connected to NC on the DDR3 (pin J9). We do not have this pin on the DDR4. Should CKE1 on LS1043 be left open or terminated?
best regards
Trond Inge
