LS1021a TAP Error

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LS1021a TAP Error

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Contributor II

I am bringing up a custom board which very closely resembles the TWR evaluation board.  The attached Flash and DDR3L are identical.  We also use the same clocking IC and scheme. I've verified the clocks and power to the LS1021a

I can successfully "Erase and Program" the TWR evaluation board with Codewarrior 10.0.7 using an USB attached Codewarrior TAP.  When I execute the same programming task (in this case, just a write of the RCW) when attached to our custom board I get the following error:

Error: Connect failed.

Unknown protocol error (CCSProtocolPlugin)

Error: Connect failed.

The "TX/RX" light on the Codewarrior TAP is blinking green when I'm not executing the task. When I execute the task it briefly blinks red. The "Run/Pause" light on the Codewarrior TAP is constant red.

Any suggestions on what might be causing this?

17 Replies

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NXP Employee
NXP Employee

You likely have no RCW in flash. This is a classic chicken and egg scenario with the processors. They need a valid RCW to come out of reset but if you don't have a valid RCW you can't program flash. 

With a blank flash, you still need to provide an RCW. This could be done through pre-programmed flash, forcing a valid RCW through JTAG, or changing the cfg_rcw_src pins to force the use of a hard coded RCW. 

Please try to change your pin strappings to a valid hard coded RCW (I'd suggest 0x9A if your sysclk = 100MHz) and try again. 

Remember to change the pin strapping back to what you had, after you program the RCW, in order to enable the processor to come out of reset using your intended RCW.

   rcw.png

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Contributor I

Hi Paul,

We are experiencing a similar issue as described in this thread. We have a hardwired RCW CFG setting as shown below, for booting from eMMC.

RCW source hard strapping on target board

 

So my question is how do we program a virgin, un-programmed board using JTAG tools, if there is no RCW to begin with? Is it possible to override the RCW strapping settings as described below?

RCW override

 

https://t.sidekickopen80.com/s1t/c/5/f18dQhb0S7lM8dDMPbW2n0x6l2B9nMJN7t5X-FdSD1CW3LjvPl4WYpmKV1fkJr1...

Other items to note here,

  1. We are using the CodeWarrior TAP (CWH-CTP-BASE-HE) with the Probe Tip CWH-CTP-CTX10-YE for flashing the LS1021A device.
  2. The clock synthesizer is strapped for 100 MHz system and DDR clocks.
  3. It is currently not possible to dynamically reassign the CFG_RCW_SRC pins.

A step by step guide for programming a blank board will be greatly appreciated.

Thank you

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NXP Employee
NXP Employee

Please try using RCW override option from CW (you can find info into Targeting manual available in \ARMv7\Help\PDF\) The problem might be because of missing/incorrect RCW on your board.

Adrian

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Contributor II

The Targeting Manual in that folder for me (v10.0.7) doesn't mention RCW override but I followed this step by step video:

How to use QorIQ RCW Override CodeWarrior|NXP

I ran this first on the TWR evaluation board because I wanted to verify it works.

When I get to the last step to debug, I get the following error:

     "Failed to correctly configure the JTAG chain."

This is for a known good working TWR board.

I can debug on it fine, but can't get the RCW override to work based on the video I linked above.

Is there a better source for RCW override instruction?

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NXP Employee
NXP Employee

Please refer to AN5184_Programing_SD_MMC_ARMv7 , chapter 4.1. This section will describes the steps for using RCW override feature from CW.

Adrian

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Contributor II

Thank you Adrian.

I'm following those steps but having trouble getting the right JTAG configuration file.

Is there an easy way to read the RCW back from the TWR board so I can verify it against the JTAG configuration file I am creating?

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NXP Employee
NXP Employee

If the RCW is missing from the board, there is no way to read it.

Basically in JTAG configuration file, you have to set at least the RCW_source as below:

LS1021A (0 0x9b) (0x1000 1)

If the PLL settings on your board fit with the value of hardcoded RCW use as RCW_source, then you will be able to take control over the board and restore the RCW into flash.

Adrian

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Contributor II

Sorry if I wasn't clear.

I am testing the RCW Override on the TWR board first to verify it works there.

I follow the procedure mentioned (which is the same as the one in the video I linked earlier) but I get the following error:

          Failed to correctly configure the JTAG chain

I changed the QorIQ configuration project to build a "Binary" file instead of a "CW JTAG config (RCW only)".  The output binary matches the PBL.bin that works when written to the flash.

So I'm pretty confident my RCW values are correct, but the JTAG chain won't configure (this is all on the TWR board).

As I mentioned before, if I don't use the RCW override and just target the LS1021A the TAP connects and debugs fine.

Attached is the CW JTAG config file that is generated and then used for RCW override.

Does this look OK?

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NXP Employee
NXP Employee

CW jtag file you are trying to use is not correct. You can find jtag file under CW_ARMv7\ARMv7\ARM_Support\Configuration_Files\jtag_chains\. Also, as I said before you can use only

LS1021A (0 0x9b) (0x1000 1)

DAP

SAP2

If you are sure 0x9b hardcoded value fit your board settings.

Adrian

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Contributor II

HRESET is asserted during the POR sequence but never deasserted.

PORESET in yellow and HRESET in blue.

y-POR_RESET_b-HRESET.png

The ramp on HRESET is the power up ramp on the 1.8V to which it is pulled up (1K resistor).

Should JTAG still work if the LS1021 has not completed it's power on reset sequence?

If not, is there a way to narrow down where it is hanging in the power on sequence?

The HRESET assertion tells me it's somewhere between step 5 and 14 (based on the detailed sequence in section 4.4.1 of the Reference Manual). Is there another signal to monitor to get closer to the issue?

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NXP TechSupport
NXP TechSupport

It is needed to doublecheck that all notes after the QorIQ LS1021A Data Sheet, Table 1. Pinout list by bus are fulfilled.

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Contributor II

Thank you Adrian.

The file you referenced worked as an RCW override for the TWR board.

When I use it for our custom hardware, I get the same error:

     Failed to correctly configure the JTAG chain.

Does this mean it hasn't come out of it's Power on Reset mode correctly?

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NXP TechSupport
NXP TechSupport

Please confirm that the TWR board is accessible using the same equpment - i.e. only test board is swapped.

Compare revisions of the LS1021A processors on both boards and if they are different try to upgrade the CodeWarrior.

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Contributor II

Yes, the TWR board is accessible with the exact same equipment, only swapping the test board.

From what I can tell the versions are the same. I have LS1021ASN7KQB on our board and the version 2.0 TWR board.

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NXP TechSupport
NXP TechSupport

Please enable CCS logging from CW and also open manually CCS and activate verbose log (log v).

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Contributor II

With verbose logging I get the following output in the CCS window when I try to initiate an erase and program of the RCW:

CCS Windows Release Build 433p0

verbose logging

CCSAPI connection #1 accepted from CSSI-HP at Wed Aug 10 14:06:48 2016

check_min_version(serverh=0,*version)

  api version: 00000004 00000006

get_connection_count(serverh=0,cc_index=0,*count)

  count:1

available_connections(serverh=0,*count,*cc)

  connections:

available_connections(serverh=0,*count,*cc)

  connections:

setup_cc(serverh=0,config_string= cwtap:0 )

available_connections(serverh=0,*count,*cc)

  connections: {0,73,0xa9fe8da0}

available_connections(serverh=0,*count,*cc)

  connections: {0,73,0xa9fe8da0}

available_connections(serverh=0,*count,*cc)

  connections: {0,73,0xa9fe8da0}

cc_version(serverh=0,cc_index=0,index=7471205,*version)

get_config_chain(serverh=0,cc=0)

config_server(config_reg=0,config_data=0x000003E8)

config_chain(serverh=0,cc=0,count=3,*devlist,*generic)

  devlist: ls1020a,dap,sap2

get_config_chain(serverh=0,cc=0)

reset_to_debug(serverh=0,cc=0)

  ERROR(39): Subcore error encountered during multicore operation

parse_error_ext(coreh.{serverh=0,cc_index=0,chain_pos=0}, 39)

  error: LS1020A: Core not responding

get_subcore_error(serverh=0,cc=0,*error,*chain_pos)

  error: Core not responding

  chain_pos: 0

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NXP TechSupport
NXP TechSupport

Please also enable CCS logging in the CodeWarrior and provide the CW CCS console log.

Error 39 could indicate that the core is not operating properly - i.e. was not able to properly complete its POR.

Please doublecheck that the design complies with the AN4878 - LS1021A Design Checklist and all notes after the "Table 1. Pinout list by bus" in the QorIQ LS1021A Data Sheet are fulfilled.

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