Hello,
I'm currently looking at an issue with the LS1021a whereby the USB 3.0 port enumerates fine at both at SS & FS, but is not enumerating at HS.
Looking at the USB DP/DM pair with a scope, the LS1021A is not putting out a K-chirp during reset after the bus enumerates at FS.
Has anyone else encountered this problem?
Thanks and best regards,
Steve
Hello Steve Merritt,
USB 3.0 provides backward compatibility, any USB 3.0 port has a USB 2.0 PHY signals and additional super-speed signals section.
USB 2.0 host controllers and hubs provide capabilities so that full-speed and low-speed data can be transmitted at high speed between and the host controller and the hub, but transmitted between the hub and the device at full-speed or low-speed.
We have tested TWR-LS1021a USB 3.0 port to work at USB 2.0 mode without any problem. You could refer to TWR-LS1021a hardware design. You could download document "QorIQ LS1021A Design Checklist" from https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/qoriq-lay... to check USB PHY pin checklist.
In addition is it possible for you to program LSDK u-boot on your custom target board to do more verification? Because we have some errata fixed in u-boot source code. Eg. A-009798: USB high speed squelch threshold adjustment
If your problem remains, you could create a case in our internal system to review your hardware design.
Thanks,
Yiping