LS1021A-IOT CAAM support with IoT-gateway-platform-Release-V0.1

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LS1021A-IOT CAAM support with IoT-gateway-platform-Release-V0.1

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Contributor I

I was trying to enable hardware encryption with the lastest v0.1 SDK (20170120), but the caam module will not load. The error from the dmesg output is

[ 2.451399] caam 1700000.crypto: can't identify CAAM ipg clk: -2
[ 2.457402] caam: probe of 1700000.crypto failed with error -2

The caam driver looks for 4 clocks (mem, aclk, ipg and emi_slow) during the probe and if they are not present, it will not load. However, these clocks are not defined in the crypto section of the ls1021a.dtsi file. Should these clocks be defined and, if so, is the configuration available? Or, alternatively, should the driver be looking for the clocks on this platform? 

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9 Replies

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Contributor I

Hi

Where you find SDK 0.1 for LS1021A-IOT?

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Contributor III

If anyone still get this error, check dts and dtsi, clock names for caam module at a certain point has changed from caam_ipg to ipg. Sp check to use proper dtsi against what expectd in drivers/crypto/caam/ctrl.c

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Contributor I

Hi Yiping,

I have posted the contents of the dts files as I can't attach it in here. sorry about that. but they are same the default files of new sdk.

Thanks. 

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NXP TechSupport
NXP TechSupport

Hello Yuqian,

Would you please provide your Kernel configuration (.config)file?

Please click "Use advanced editor" on the right top to attach the file.

Thanks,

Yiping

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92 Views
Contributor I

Hi Yiping,

Thanks. Here is the kernel config file.

BTW, I figured it out how to attached a file :smileyhappy: thanks.

Yuqian

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NXP TechSupport
NXP TechSupport

Hello Yuqian,

Please don't enable "CONFIG_CRYPTO_DEV_FSL_CAAM_IMX" in your Kernel configuration file, please refer to the following definition in the Kernel source code. On QorIQ platforms, it should return NULL, only IMX platforms have the clock control.

#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
static inline struct clk *caam_drv_identify_clk(struct device *dev,
                                                char *clk_name)
{
        return devm_clk_get(dev, clk_name);
}
#else
static inline struct clk *caam_drv_identify_clk(struct device *dev,
                                                char *clk_name)
{
        return NULL;
}
#endif

I attached LS1021A default Kernel configuration file, you could configure your Kernel based on it.


Have a great day,
TIC

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Contributor I

Hi Yiping,

Seems that is a bug of SDK? We didn't enable it in the kernel, please refer below picture shows 

Screen Shot 2017-04-20 at 4.01.21 PM.png

Also, I checked the CAAM driver folder Kconfig file, seems it is fine as we absolutely not select iMX series CPU, but no idea why it was enabling

-------------

config CRYPTO_DEV_FSL_CAAM_IMX

        def_bool SOC_IMX6 || SOC_IMX7D

        depends on CRYPTO_DEV_FSL_CAAM

config CRYPTO_DEV_FSL_CAAM_LE

        def_bool (CRYPTO_DEV_FSL_CAAM_IMX || SOC_LS1021A) && !ARCH_LAYERSCAPE

        depends on CRYPTO_DEV_FSL_CAAM

 -----------

I will disable it and compare config file which you attached one and do a test now, will keep you update 

Thanks

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92 Views
NXP TechSupport
NXP TechSupport

Hello Yuqian,

Please also disable SOC_IMX6 in your Kernel configuration file.

Thanks,

Yiping

92 Views
Contributor I

Hi Yiping,

Thanks for your support, Now I got it working, will test the performance :smileyhappy: 

root@OpenWrt:/# dmesg |grep caam
[ 49.746357] caam_jr 1710000.jr: caam_read: start reading at buffer 0, idx 0
[ 49.746711] caam 1700000.crypto: fsl,sec-v5.0 algorithms registered in /proc/crypto
root@OpenWrt:/# cat /proc/interrupts
CPU0 CPU1
16: 0 0 GIC 29 Edge arch_timer
17: 18707 20463 GIC 30 Edge arch_timer
23: 9327 0 GIC 126 Level mmc0
26: 5 0 GIC 163 Level 1550000.quadspi
27: 316 0 GIC 120 Level 2180000.i2c
28: 444 0 GIC 118 Level serial
37: 0 0 GIC 165 Level sai
38: 0 0 GIC 167 Level eDMA
41: 0 0 GIC 205 Level gianfar_ptp
47: 62 0 GIC 125 Level xhci-hcd:usb1
48: 0 0 GIC 213 Level ls-pcie-pme
49: 0 0 GIC 215 Level aerdrv
50: 0 0 GIC 214 Level ls-pcie-pme
51: 0 0 GIC 216 Level aerdrv
52: 0 0 GIC 211 Level MSI-GROUP
53: 0 0 GIC 212 Level MSI-GROUP
54: 0 0 GIC 123 Level PCIe PME
55: 0 0 GIC 124 Level PCIe PME
56: 0 0 GIC 197 Edge phy_interrupt
57: 0 0 GIC 182 Level eth0_g0_tx
58: 0 0 GIC 184 Level eth0_g0_rx
59: 0 0 GIC 185 Level eth0_g0_er
60: 0 0 GIC 186 Level eth0_g1_tx
61: 0 0 GIC 187 Level eth0_g1_rx
62: 0 0 GIC 188 Level eth0_g1_er
69: 1 0 GIC 135 Level 1710000.jr
70: 0 0 GIC 136 Level 1720000.jr
71: 0 0 GIC 137 Level 1730000.jr
72: 0 0 GIC 138 Level 1740000.jr
IPI0: 0 0 CPU wakeup interrupts
IPI1: 0 0 Timer broadcast interrupts
IPI2: 9745 11337 Rescheduling interrupts
IPI3: 0 0 Function call interrupts
IPI4: 11 82 Single function call interrupts
IPI5: 0 0 CPU stop interrupts
IPI6: 0 0 IRQ work interrupts
IPI7: 0 0 completion interrupts
Err: 0

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