There seems to be a discrepancy between the document TWR-LS1021A Reference Manual (Rev. 1 07/15) and the QorIQ LS1021A Data Sheet (Rev. 3 05/16) with regard to the SerDes usage. Figure 1. of the Data Sheet shows that only two Ethernet Controllers are associated with only 2 lanes the SerDes, whereas the Reference Manual shows all three Ethernet Controllers can be used with 3 lanes of the SerDes.
Please help clarify.
Thanks,
Howard
> Shouldn't the following be 10/100/1000 Mbps?
You have a keen eye :smileyhappy:
Of course you're right again.
I am designing my own board, so I need to know the chip's capability wrt SGMII, not the board's feature. But, I think I know the answer now. Thx
Btw, Shouldn't the following be 10/100/1000 Mbps? (10/100/1G does not work either :-) ).
• Ethernet (from Board features)
— One onboard RGMII 10 G/100 G/1 G Ethernet port.
Thanks,
Howard
Take a look at "Figure 1-1. LS1021A block diagram" of the "TWR-LS1021A Reference Manual" document, and compare that to "Figure 1. LS1021A block diagram" of the "QorIQ LS1021A Data Sheet" document, you will understand what I mean.
Thanks,
Howard
You are right.
Please consider that wording just before the figure is correct - i.e. 1.3 Board features:
• Ethernet
— One onboard RGMII 10 G/100 G/1 G Ethernet port
— IEEE 1588 test header on board
— Two onboard SGMII 10 G/100 G/1 G Ethernet ports
> whereas the Reference Manual shows all three Ethernet Controllers can be used with 3 lanes of the SerDes.
What exactly do you mean?