We are using a design based upon the LS1012AFRWY reference design, but using a TI DP83867CS as the ethernet phy.
After some initial issues the ethernet interface is working as expected. The interface between the ethernet phy and the LS1012A is using 4-wire SGMII.
In some reference designs, the phy's local clock is no longer isolated, but instead driven by the LS1012A's 25MHz clock via a buffer (LS1012ARDB changes from version C to D). Is this the recommendation for our configuration as I see some errata for other QoriQ processors to do with SGMII and clocking?
Also, does the LS1012A's SGMII interface support auto-negotiation?