JTAG connections on PCIe to FPGA

cancel
Showing results for 
Search instead for 
Did you mean: 

JTAG connections on PCIe to FPGA

1,713 Views
fzhang
Contributor II

General question on how to connect JTAG pins from LS1021A to Altera FPGA through PCIe x4 bus? Planning to link LS1021A to FPGA (Arria V), but don't know how to connect the JTAG pin on the bus to the micro processor in order to program the FPGA through the micro. Did not found it anywhere on the reference manual either.

Please help if any suggestions or where to the right documents are. Thanks

Labels (1)
Tags (3)
3 Replies

310 Views
alexander_yakov
NXP TechSupport
NXP TechSupport

I do not think we have ready-to-use solution for connecting LS1021A' JTAG pins to Arria V FPGA via PCIe bus, this is not a typical use case. Looking to our LS1021A-based development board, I see we do not use these signals on PCIe connector.

If the question is how to implement this functionality, than I think usual GPIO pins must be used, and please do not forget about voltage level difference, use voltage level shifters if necessary.


Have a great day,
Alexander

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

310 Views
fzhang
Contributor II

Thank you, Alexander,

That answers my question. Using GPIOs for JTAG connections on PCIe, not sure how the Linux will support the JTAG link over PCIe though.

Anyway, what I am looking into is to use LS1021A with Altera Arria V on a main board. The tasks for LS1021A is to communicate with FPGA through PCIe x4, even configure it through JTAG. Also use the GigE to connect to a PC. USB, HDMI and SD card ports to LS1021A.

I looked at the Tower board of this device. It seems more complicated than what I thought. First of all the CPLD controls the power up and reset sequences, LCD display and more. I don't know if it's possible to run the micro without the CPLD. If not, can the programming codes for the CPLD be shared with us.

Thanks,

FZ

310 Views
alexander_yakov
NXP TechSupport
NXP TechSupport

I'm not sure you need any kind of specific support in Linux, if the external device is connected to GPIO pins.

I'm quite sure general GPIO driver will be enough.

Yes, board design source files are available, but NDA must be in place. Please contact your local NXP representative to sign NDA and get this design collateral.

Our distributors page:

Distributor Network|NXP 


Have a great day,
Alexander

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------