Issue with mmc command set

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Issue with mmc command set

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amarnathmb
Contributor III
Hi All,
 
I'm working on a T1042 based custom board that has an onboard eMMC (8GB, GLS85VM1008A-M-I-LFWE-ND202) connected to eSDHC port. I have successfully booted uboot 2019.07 (DNEX) from NOR flash on my board.
 
I'm facing an issue with mmc command set, when I issue an 'mmc list' command once the board boots up it lists " FSL_SDHC: 0 " and 'mmc info' lists the details of the onboard eMMC.
 
The 'mmc read' command works fine for me without any error, but when I issue an 'mmc write' command it returns error "0 blocks written: ERROR".

Why is it so? Am I doing something wrong?
 
Another observation is that, any mmc command after issuing  'mmc dev 0 0'  prints nothing on the console, but 'mmc list' still lists the " FSL_SDHC: 0 ".
Thanks in advance for all your support.
Regards,
Amarnath MB
Please find the below u-boot log for detail (enabled CONFIG_MMC_TRACE).
U-Boot 2019.07 (Dec 21 2019 - 17:10:04 +0530)

CPU0:  T1042E, Version: 1.1, (0x85280211)
Core:  e5500, Version: 2.1, (0x80241021)
Clock Configuration:
       CPU0:1200 MHz, CPU1:1200 MHz, CPU2:1200 MHz, CPU3:1200 MHz,
       CCB:500  MHz,
       DDR:533.333 MHz (1066.667 MT/s data rate) (Asynchronous),
       IFC:250  MHz
       QE :250  MHz
       FMAN1: 500 MHz
       QMAN:  250 MHz
       PME:   250 MHz
L1:    D-cache 32 KiB enabled
       I-cache 32 KiB enabled
Reset Configuration Word (RCW):
       00000000: 0a10000c 0c000000 00000000 00000000
       00000010: 00000002 00400002 ec027000 01000000
       00000020: 00000000 00010001 60000000 00028000
       00000030: 00000200 00165005 00000000 00000000
Board: VPX-135
I2C:   ready
DRAM:  Initializing DDR....
Configuring DDR for 1066.667 MT/s data rate
Setting DDR register values...
2 GiB left unmapped
SDRAM test phase 1:
SDRAM test phase 2:
SDRAM test passed.
2 GiB (DDR4, 64-bit, CL=12, ECC on)
Flash: 512 MiB
L2:    256 KiB enabled
Corenet Platform Cache: 256 KiB enabled
Using SERDES1 Protocol: 0 (0x0)
Enabling all cpus
MMC:   FSL_SDHC: 0
Loading User and Factory Environments...

*** Warning - FACTORY ENVIRONMENT bad CRC, using default factory environment

Firmware 'Microcode version 0.0.1 for T1040 r1.0' for 1040 V1.0
QE: uploading microcode 'Microcode for T1040 r1.0' version 0.0.1
Waiting 1000 ms on enumerating the PCIe bus...
PCIe1: Root Complex, @ 5 Gbps x4 gen2, regs @ 0xfe240000
PCIe1: Bus 00 - 01
PCIe2: Root Complex, @ 2.5 Gbps x4 gen1, regs @ 0xfe250000
  03:00.0     - 10e3:8114 - Bridge device
PCIe2: Bus 02 - 04
In:    serial
Out:   serial
Err:   serial
SERDES Reference : 0x0
Temperature init Done

*** Warning - U-boot image is Updated

Net:   Initializing Fman
Fman1: Uploading microcode version 106.4.18
Could not get PHY for FSL_MDIO0: addr 2
Failed to connect
Could not get PHY for FSL_MDIO0: addr 3
Failed to connect
FM1@DTSEC4, FM1@DTSEC5 [PRIME]
POST vid PASSED
POST i2c PASSED
POST rtc Sun Feb  1 2020 00:00:00 :: PASSED
POST ethernet FM1@DTSEC4 is not a known ethernet
Error: port FM1@DTSEC4 not registered with core -FAILED
POST flash PASSED
POST nvram PASSED
POST temp Init Done
Core Temperature : 51'C :: PASSED
VPX-135 #
VPX-135 #
VPX-135 # mmc list
FSL_SDHC: 0
VPX-135 # mmc info
MSPL: mmc_init
MSPL : mmc_start_init entry
CMD_SEND:0
                ARG                      0x00000000
                MMC_RSP_NONE
CMD_SEND:8
                ARG                      0x000001aa
                RET                      -110
CMD_SEND:55
                ARG                      0x00000000
                RET                      -110
CMD_SEND:0
                ARG                      0x00000000
                MMC_RSP_NONE
CMD_SEND:1
                ARG                      0x00000000
                MMC_RSP_R3,4             0x40ff8080
CMD_SEND:1
                ARG                      0x40300000
                MMC_RSP_R3,4             0xc0ff8080
MSPL : mmc_get_op_cond exit
CMD_SEND:2
                ARG                      0x00000000
                MMC_RSP_R2               0xf8010056
                                         0x4d303130
                                         0x42aad20f
                                         0x60e15600

                                        DUMPING DATA
                                        000 - 56 00 01 f8
                                        004 - 30 31 30 4d
                                        008 - 0f d2 aa 42
                                        012 - 00 56 e1 60
CMD_SEND:3
                ARG                      0x00010000
                MMC_RSP_R1,5,6,7         0x00000500
CMD_SEND:9
                ARG                      0x00010000
                MMC_RSP_R2               0xd07f0132
                                         0x1f5903ff
                                         0xffffffff
                                         0x92400000

                                        DUMPING DATA
                                        000 - 32 01 7f d0
                                        004 - ff 03 59 1f
                                        008 - ff ff ff ff
                                        012 - 00 00 40 92
CMD_SEND:7
                ARG                      0x00010000
                MMC_RSP_R1,5,6,7         0x00000700
CMD_SEND:8
                ARG                      0x00000000
                MMC_RSP_R1,5,6,7         0x00000900
CMD_SEND:6
                ARG                      0x03b70200
                MMC_RSP_R1b              0x00000900
CMD_SEND:13
                ARG                      0x00010000
                MMC_RSP_R1,5,6,7         0x00000900
CURR STATE:4
CMD_SEND:6
                ARG                      0x03b90100
                MMC_RSP_R1b              0x00000900
CMD_SEND:13
                ARG                      0x00010000
                MMC_RSP_R1,5,6,7         0x00000900
CURR STATE:4
CMD_SEND:8
                ARG                      0x00000000
                RET                      -70
CMD_SEND:6
                ARG                      0x03b70000
                MMC_RSP_R1b              0x00000900
CMD_SEND:13
                ARG                      0x00010000
                MMC_RSP_R1,5,6,7         0x00000900
CURR STATE:4
CMD_SEND:6
                ARG                      0x03b70100
                MMC_RSP_R1b              0x00000900
CMD_SEND:13
                ARG                      0x00010000
                MMC_RSP_R1,5,6,7         0x00000900
CURR STATE:4
CMD_SEND:6
                ARG                      0x03b90100
                MMC_RSP_R1b              0x00000900
CMD_SEND:13
                ARG                      0x00010000
                MMC_RSP_R1,5,6,7         0x00000900
CURR STATE:4
CMD_SEND:8
                ARG                      0x00000000
                MMC_RSP_R1,5,6,7         0x00000900
CMD_SEND:8
                ARG                      0x00000000
                MMC_RSP_R1,5,6,7         0x00000900
CMD_SEND:16
                ARG                      0x00000200
                MMC_RSP_R1,5,6,7         0x00000900
CMD_SEND:17
                ARG                      0x00000000
                MMC_RSP_R1,5,6,7         0x00000900
Device: FSL_SDHC
Manufacturer ID: f8
OEM: 100
Name: VM010
Bus Speed: 52000000
Mode: MMC High Speed (52MHz)
Rd Block Len: 512
MMC version 4.4.1
High Capacity: Yes
Capacity: 7.3 GiB
Bus Width: 4-bit
Erase Group Size: 4 MiB
HC WP Group Size: 8 MiB
User Capacity: 7.3 GiB
Boot Capacity: 512 KiB ENH
RPMB Capacity: 512 KiB ENH
VPX-135 # mmc read 1000 0 1
MSPL: mmc_init

MMC read: dev # 0, block # 0, count 1 ... CMD_SEND:16
                ARG                      0x00000200
                MMC_RSP_R1,5,6,7         0x00000900
CMD_SEND:17
                ARG                      0x00000000
                MMC_RSP_R1,5,6,7         0x00000900
1 blocks read: OK
VPX-135 # md 1000
00001000: 00000000 00000000 00000000 00000000    ................
00001010: 00000000 00000000 00000000 00000000    ................
00001020: 00000000 00000000 00000000 00000000    ................
00001030: 00000000 00000000 00000000 00000000    ................
00001040: 00000000 00000000 00000000 00000000    ................
00001050: 00000000 00000000 00000000 00000000    ................
00001060: 00000000 00000000 00000000 00000000    ................
00001070: 00000000 00000000 00000000 00000000    ................
00001080: 00000000 00000000 00000000 00000000    ................
00001090: 00000000 00000000 00000000 00000000    ................
000010a0: 00000000 00000000 00000000 00000000    ................
000010b0: 00000000 00000000 00000000 00000000    ................
000010c0: 00000000 00000000 00000000 00000000    ................
000010d0: 00000000 00000000 00000000 00000000    ................
000010e0: 00000000 00000000 00000000 00000000    ................
000010f0: 00000000 00000000 00000000 00000000    ................
VPX-135 # mmc write 1000 0 1
MSPL: mmc_init

MMC write: dev # 0, block # 0, count 1 ... MSPL: mmc_get_dev
MSPL: mmc_init
CMD_SEND:16
                ARG                      0x00000200
                MMC_RSP_R1,5,6,7         0x00000900
CMD_SEND:24
                ARG                      0x00000000
                RET                      -110
mmc write failed
0 blocks written: ERROR
VPX-135 # mmc list
FSL_SDHC: 0 (eMMC)
VPX-135 # mmc dev 0
MSPL: mmc_init
MSPL : mmc_start_init entry
CMD_SEND:0
                ARG                      0x00000000
                MMC_RSP_NONE
CMD_SEND:8
                ARG                      0x000001aa
                RET                      -110
CMD_SEND:55
                ARG                      0x00000000
                RET                      -110
CMD_SEND:0
                ARG                      0x00000000
                MMC_RSP_NONE
CMD_SEND:1
                ARG                      0x00000000
                MMC_RSP_R3,4             0xc0ff8080
MSPL : mmc_get_op_cond exit
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
VPX-135 # mmc list
FSL_SDHC: 0
VPX-135 # mmc info
MSPL: mmc_init
MSPL : mmc_start_init entry
CMD_SEND:0
                ARG                      0x00000000
                MMC_RSP_NONE
CMD_SEND:8
                ARG                      0x000001aa
                RET                      -110
CMD_SEND:55
                ARG                      0x00000000
                RET                      -110
CMD_SEND:0
                ARG                      0x00000000
                MMC_RSP_NONE
CMD_SEND:1
                ARG                      0x00000000
                MMC_RSP_R3,4             0xc0ff8080
MSPL : mmc_get_op_cond exit
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
VPX-135 # mmc read 1000 0 1
MSPL: mmc_init
MSPL : mmc_start_init entry
CMD_SEND:0
                ARG                      0x00000000
                MMC_RSP_NONE
CMD_SEND:8
                ARG                      0x000001aa
                RET                      -110
CMD_SEND:55
                ARG                      0x00000000
                RET                      -110
CMD_SEND:0
                ARG                      0x00000000
                MMC_RSP_NONE
CMD_SEND:1
                ARG                      0x00000000
                MMC_RSP_R3,4             0xc0ff8080
MSPL : mmc_get_op_cond exit
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
CMD_SEND:2
                ARG                      0x00000000
                RET                      -110
VPX-135 #
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amarnathmb
Contributor III

Hi all,

There is a WP_IN bit in DCFG_CSSR_SDHCPCR register to invert the polarity of SDHC_WP pin in eSDHC. After setting this bit to '1' in our uboot code we are able to successfully write in to mmc. 

Regards,

Amarnath MB

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amarnathmb
Contributor III

Hi all,

After some debugging i found that SDHC_WR pin of T1042 and WR# of eMMC are tied together in hardware. Currently these signals are pulled high, so that eMMC takes it as write enabled and T1042 eSDHC takes it as write protected. That may be why the 'mmc write' call is failing. Currently there is no way to isolate any of these signals as they are routed through inner layers, but our hardware team has to come up with a solution.

I'm still not able to find out why mmc commands return nothing after issuing 'mmc dev 0 0' command?

Regards,

Amarnath MB

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amarnathmb
Contributor III

Hi all,

There is a WP_IN bit in DCFG_CSSR_SDHCPCR register to invert the polarity of SDHC_WP pin in eSDHC. After setting this bit to '1' in our uboot code we are able to successfully write in to mmc. 

Regards,

Amarnath MB

View solution in original post

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yipingwang
NXP TechSupport
NXP TechSupport

Please refer to "5.14.2 eSDHC system-level recommendations" in AN4825.pdf which could be downloaded from QorIQ® T1042 | NXP .

Please add the following in drivers/mmc/mmc.c to get detailed communication information.

#define  DEBUG

#define CONFIG_MMC_TRACE 

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