Hello,
I am currently using cache locking on both D and I caches on the T2080 board (e6500 cores).
The locking works great and can be validated with a T32 debugger from Lauterbach.
Now here is my issue:
When flash invalidating (ICFI and NOT ICLFC) the instruction cache, all lines a marked as invalid. The locked lines are invalid but are still marked as locked on the debugger, so no issue at this point.
However, as the program executes, invalid locked lines are being gradually replaced by new instruction (that are not supposed to be locked). During the replacement, the line seems to be unlocked as is appears valid and unlocked with new data on the debugger.
Important notes:
- When disabling flash invalidation of the instruction the caches (just skipping the function that flash invalidates), we have no issue.
- I only observed this issue on I-Caches.
- We don't use selective unlocking instruction in our project. Locking happens at initialization and the only cache maintenance we do is flash invalidation using ICFI bit in cache control register.
So my questions are:
Is it a normal behavior? How to avoid replacement of locked invalid lines?
Find attached:
- a first screenshot (no_inval.png) of cache content extract during execution without flash invalidating the cache
- a second one (after_inval.png) just after flash invalidation. Lines are not valid but still locked (which is expected).
- a third one (after_inval_exec.png) after letting the system execute and before the next flash invalidation. You will see that some locked lines have been replaced with non locked data.
In these screenshots, locked data are always after 0xA0000000 and are replaced by data under this limit (which is non-locked code). L means locked, V means valid.
Best regards,
Alexy Torres
