IFC and memory stall on multi core

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IFC and memory stall on multi core

162 Views
eduard_stefes
Contributor I

Hi,

we use the LS1020a QoriQ and have something connected via IFC GPCM ASIC mode. Currently we run into race conditions then independent parts of the software try to read via IFC at the same time. Chapter 24 of LS1021ARM.pdf does not mention anything about memory stalling.

my question:

Is it possible to stall both cores when one core is doing an operation via IFC or does this need to be handled via software mutexes?

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3 Replies

84 Views
eduard_stefes
Contributor I

This is not what we see. here a detailed description of our problem:

Setup:

+----+  read#1        +--------+
|CPU0+------+         |        |                 +---------+
+----+      +-------->+ IFC    |                 | Device  |
                      | mapped |   +-------+     |         |
+----+      +-------->+ memory +---> IFC   +---->+         |
|CPU1+------+         |        |   +-------+     |         |
+----+  read#2        |        |                 +---------+
                      |        |
                      +--------+


Problem:
- the Software issues read#1 on cpu0

- cpu0 stalls and waits for read to finish

- software issues read#2 on cpu1

- even trough read#1 is still in progress the IFC starts the next read and does not wait for read#0 to finish

=> the stall on cpu0 is not release => the system crashes

Possible solutions:

- stall both cpus then read#1 happens.

- implement a software mutex for the complete IFC mapped memory area (this is hard because we use IFC to access multiple devices).

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Bulat
NXP TechSupport
NXP TechSupport

Are you able to look at IFC behavior with a scope or a logic analyser? Do you see two different CS's are asserted simultaneously?

Regards,

Bulat

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Bulat
NXP TechSupport
NXP TechSupport

I do not understand the problem with "memory stalling". The IFC will execute both requests from both cores in the order as they come. No "stall" condition is expected.

Regards,

Bulat

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