I am bringing up our T2081 design. WE need to use two PCIe ports x4 and we have selected SRDS_PR TCL_S1 =0xAA

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I am bringing up our T2081 design. WE need to use two PCIe ports x4 and we have selected SRDS_PR TCL_S1 =0xAA

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ioxos
Contributor I

When the T2081 fetch its RCW, SerDes1 PLL 1 is not locking because we supply 100MHz on

SD1_CLK1 and SD1_CLK2.  (HRST_REQn asserted after RCW read from NOR Flash)

- We need PCIe4_x4  Gen3 and PCIe3_x4 Gen2.

Do you have a workaround to operate with SD1_CLK1 and SD1_CLK2 at 100MHz ?

I can live with PCIe4_x4  Gen2 (in place of Gen3)

NOTA : In our design we are not able to supply 155MHz on SD1_CLK1

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ioxos
Contributor I

Hello,

Find attached the new RCW patched

Additional relevant info.

I read the DCFG_CCSR_PORSR1 register and I get value = 0x13ffff7f.

with XVDD_SEL = '0'. This looks to me wrong, I am expecting '1' because

T2081 pin ASLEEP has a 4K7 pull-up resistor and should configure XVDD_SEL = '1'.

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ioxos
Contributor I

Find attached RCW

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ufedor
NXP TechSupport
NXP TechSupport

In the provided "rcw_aa_1200MHz.bin" RCW[168]=SRDS_PLL_PD_S1_PLL1=1 and RCW[169]=SRDS_PLL_PD_S1_PLL2=0, but these bits have to be set vice-versa - i.e. PLL1 must be enabled.

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ioxos
Contributor I

Hello,

We have modified the RCW as suggested but  HRST_REQn is asserted after RCW read from NOR Flash.

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ufedor
NXP TechSupport
NXP TechSupport

Please provide binary image of the modified RCW.

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ufedor
NXP TechSupport
NXP TechSupport

The SD1_CLK1=100MHz is a valid clock for the SRDS_PR TCL_S1 =0xAA - refer to the QorIQ T2080 Reference Manual, Table 19-4. Valid SerDes Reference Clocks and RCW Encodings.

Please provide binary image of the RCW being used.

Confirm that you have checked that the RCW is correctly read from its source.

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ioxos
Contributor I

Hello,

YES, the RCW is read correctly, we have verified it at the IFC Bus level and also confirmed by UBOOT.

NOTA : To have UBOOT up and running I do not use HRST_REQn -> HRSTn to the T2081

I am using following file .rcw to generate the RCW

/*

* T2081QDS RCW for SerDes Protocol 0xAA

*

* 2G configuration -- 2 RGMII + PCIE x4 (slot1) + PCIE x4 (slot2)

*

* Frequencies:

*

* SYSCLK: 66.66 MHz        (SW3[1:4] = 0000)

* DDRCLK: 133.33MHz        (SW3[5:6] = 11)

* SD1_REF1 CLK: 156.25 MHz (SW4[1:2] = 10)

* SD1_REF2 CLK: 100 MHz    (SW4[3:4] = 11)

* SD2_REF1 CLK: 100 MHz    (SW4[5:6] = 11)

* SD2_REF2 CLK: 100 MHz    (SW4[7:8] = 11)

*

* Core -- 1200 MHz (Mul 18)

* Platform -- 533 MHz (Mul 8)

* DDR -- 800 MHz (1600 MT/s) (Mul 12)

* FMAN -- 533 MHz (HWA_CGA_M1_CLK_SEL=5)

*

* RGMII1: MAC3

* RGMII2: MAC4

* XFI:    NULL

*

* Slot  Card

* 1     PCIe4 x4 (8/5/2.5 Gbps)

* 2     PCIe3 x4 (5/2.5 Gbps)

* 3     NULL

* 4     NULL

* 5     NULL

* 6     NULL

* 7     NULL

*

* PBI source is NOR

*/

#include <../t2080qds/t2080.rcwi>

SYS_PLL_RAT=8

MEM_PLL_RAT=12

CGA_PLL1_RAT=18

CGA_PLL2_RAT=21

HWA_CGA_M1_CLK_SEL=5

HWA_CGA_M2_CLK_SEL=4

FM_MAC_RAT=1

SRDS_PLL_PD_S1=0

SRDS_PRTCL_S1=0xaa

SRDS_PLL_REF_CLK_SEL_S1=0          

SRDS_DIV_PEX_S1=0                 

PBI_SRC=14

BOOT_LOC=24

IFC_MODE=39

DRAM_LAT=1

UART_BASE=6

IRQ_BASE=511

Regards

Joel

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ufedor
NXP TechSupport
NXP TechSupport

Please provide binary image of the RCW being used.

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ioxos
Contributor I
How can I send yyou the binary image
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ufedor
NXP TechSupport
NXP TechSupport

By attaching it to the response.

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