How to disable or mask system call interrupt on PowerPC e500 cores.

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How to disable or mask system call interrupt on PowerPC e500 cores.

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saqlainraza
Contributor I

Hi,

Is there a way by which I can disable or mask the system call interrupt on an e500 core. The e500 core reference manual describes the enabling and disabling of different interrupts via the MSR register but I cannot see any bit for changing the status of a system call interrupt.

Can someone please help me out in this regard.

Thanks,

Bunny.

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promwadengineer
Contributor I

Hi,

Processor Freescale P1020 e500 core based.

Linux is run on core1.

Preemptive mode is disabled.

I have a problem: spin_lock_irqsave() and spin_lock_irqrestore() don't work correctly.

In my configuration spin_lock_irqsave() does nothing except block/unblock all external interrupts on e500 core.

static inline void raw_local_irq_save_ptr(unsigned long *flags)

{

    unsigned long msr;

    msr = mfmsr();

    *flags = msr;

    asm __volatile__("wrteei 0": : :"memory");

}

After calling the instruction "wrteei 0" on CPU core1 interruptions still continue to occur (Test on UART interrupts).

Also tried set MSR[EE]=0 and MSR=0 through instruction "mtmsr". After reading register MSR (throught "mfmsr") all bits remain in previous writed state. But interrupt still continue to occur.

Source code used to write in MSR register:

    unsigned long msr_value = 0;

    asm volatile("mtmsr %0" : : "r" (msr_value) : "memory");

How to repair spin_lock_irqsave() and spin_lock_irqrestore()?

What could be the problem?

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scottwood
NXP Employee
NXP Employee

Don't reply to an old thread to ask a new and different question -- start a new thread.

There is nothing wrong with spin_lock_irqsave, wrtee, etc.  How are you determining that the interrupts are happening while EE is cleared?  Are you sure they're happening on the same core?  Did you somehow route the interrupt to critical input or machine check (Linux does not do this)?

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scottwood
NXP Employee
NXP Employee

More generally, masking applies to asynchronous interrupts (with occasional exceptions such as debug).  You usually cannot mask synchronous exceptions such as TLB errors, program checks, and system calls.  Why would you want to?  What would you expect to happen if an sc instruction is executed while masked?

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saqlainraza
Contributor I

Thanks, for the response. Basically I am working on a piece of code that calls the "sc" or system call instruction in a while(1) loop for implementing something similar to semi-hosting for ARM. The code keeps running fine in while (1) loop until I suspend its execution. Now when I resume the execution, the system call interrupt is not generated. I was thinking if there was some problem that the system call interrupt gets masked and thus is not generated.

Any help or suggestions regarding this ? Can you plz describe that how the context should be restored after a system call interrupt ? Currently I am restoring the context by writing the value of SRR0 to PC and SRR1 to MSR register ?

Thanks.....

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scottwood
NXP Employee
NXP Employee

The rfi instruction should be used to move SRR0 to PC and SRR1 to MSR -- you should not try to do it manually.

I suggest using an external debugger to see what's going on (e.g. single step through the instructions).  What specifically do you mean by "suspend/resume its execution", and what specifically happens instead when "the system call interrupt is not generated"?

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r8070z
NXP TechSupport
NXP TechSupport


Have a great day,

The system call it is just core instruction (sc). It is executed by core - i.e. from my point of view it does not interrupt anything. From other side interrupt flow allows the interrupt handler (ISR) to run in a different privilege level than before. I.e. it is well defined, hardware assisted way from the privilege prison every process runs in. The system call instruction gives software possibility to use this way.

Let assume the external interrupts is disabled (MSR[EE]=0) while there is external interrupt event for this core. When the core executes instruction which enables external interrupts (sets MSR[EE]=0) it will get the interrupt request and jump to the interrupt handler.

Like that when the core executes system call instruction it jump to the system call interrupt handler. So we may imagine that system call interrupt is always pending and disabled until core does not enable it.

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