How PBL identifies u-boot location in NOR flash from PBI commands?

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How PBL identifies u-boot location in NOR flash from PBI commands?

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veerendranathj
Contributor III

Hi,

PBL identifies boot medium using config source switches then by default RCW starts at 0x0 of NOR flash.... but in NOR flash memory map u-boot is located in 0xEFF80000.

How PBL knows from where u-boot boot code(4kb code) starts for copying it to boot page?

Below is the RCW+PBI code in NOR flash of P2041RDB....

e8000000: aa55aa55 010e0100 4c580000 00000000  -> RCW preamble

e8000010: 58540000 00000000 648ea0c1 c3c02000

e8000020: de800000 40000000 00000000 00000000

e8000030: 00000000 d0030f07 00000000 00000000

e8000040: 00000000 00000000 091380c0 000009c4 -> PBI commands started at "e800004c"

e8000050: 09000010 00000000 091380c0 000009c4 -> Alternate config space high addr register setup

e8000060: 09000014 00000000 091380c0 000009c4 -> Alternate config space low addr registers setup

e8000070: 09000018 81d00000 091380c0 000009c4 -> Alternate config space attribute register setup

e8000080: 890b0050 00000002 091380c0 000009c4 -> Moving values to alternative config space, But here onwords I couldn't get exact meaning of PBI commands

e8000090: 890b0054 00000002 091380c0 000009c4 -> How PBL setting CPC SRAM as bootpage

e80000a0: 890b0058 00000002 091380c0 000009c4 -> How PBL knows from which location of NOR flash u-boot image should be copied to 4k bootpage space?

e80000b0: 890b005c 00000002 091380c0 000009c4

e80000c0: 890b0090 00000002 091380c0 000009c4

e80000d0: 890b0094 00000002 091380c0 000009c4

e80000e0: 890b0098 00000002 091380c0 000009c4

e80000f0: 890b009c 00000002 091380c0 000009c4

e8000100: 890b0108 00000012 091380c0 000009c4

e8000110: 89021008 0000f000 091380c0 000009c4

e8000120: 89021028 0000f000 091380c0 000009c4

e8000130: 89021048 0000f000 091380c0 000009c4

e8000140: 89021068 0000f000 091380c0 000009c4

e8000150: 09138000 00000000 08138040 d5e599a1 -> PBI command for CRC check

Thanks and Regards,

Veerendranath

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ufedor
NXP TechSupport
NXP TechSupport

Please refer to the P2040 QorIQ Integrated Multicore Communication Processor Family Reference Manual, 13.3.6 Options register n layout for GPCM Mode (eLBC_ORgn) - after reset CS0 is valid BR0[V]=1 and OR0[AM]=0 - i.e. the whole eLBC 32-bit address space will be "filled" by copies of the 128MB NOR Flash connected to CS0.

4 kB of the uppermost "copy" of the boot device will be exposed in the Boot Page (RM, 4.3.3 Boot Space Translation), so the core will be able to fetch and execute its first instructio from address 0x0_FFFF_FFFC.

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ufedor
NXP TechSupport
NXP TechSupport

Please note that NOR Flash is directly mapped into the processor's address space as a whole, so it is possible to execute U-Boot code from the NOR Flash directly (in contrary to NAND Flash, which is a block device, thus U-Boot code has to be read from NAND to CPC SRAM and executed from there).

You wrote:

> -> PBI commands started at "e800004c"

The PBI commans from this comment up to the end of the PBL implement errata workarounds - please refer to the PBL source:

sdk/rcw.git - Freescale PowerPC Reset Config Word (RCW) Tree

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veerendranathj
Contributor III

I have some confusion here...

P2041RDB NOR Flash Memory Map.PNG

1) according to  P2041RDB NOR flash(current Bank) memory map RCW is starts at 0x0 and U-Boot is located end of the NOR flash i.e. "0xeff80000".

How PBL knows U-Boot location after RCW read and write configuration? I mean how processor 4KB bootspace will be mapped to U-boot location?

2) When board booted to u-boot console.. NOR Flash memory map will be E8000000-EFFFFFFF... But  bootspace memory map is FFFFF000-FFFFFFFF(4kb). If Bootspace code execution happening from NOR flash it self.. How NOR flash will be remapped to "E8000000-EFFFFFFF"?

Regards,

Veerendranath

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ufedor
NXP TechSupport
NXP TechSupport

Please refer to the P2040 QorIQ Integrated Multicore Communication Processor Family Reference Manual, 13.3.6 Options register n layout for GPCM Mode (eLBC_ORgn) - after reset CS0 is valid BR0[V]=1 and OR0[AM]=0 - i.e. the whole eLBC 32-bit address space will be "filled" by copies of the 128MB NOR Flash connected to CS0.

4 kB of the uppermost "copy" of the boot device will be exposed in the Boot Page (RM, 4.3.3 Boot Space Translation), so the core will be able to fetch and execute its first instructio from address 0x0_FFFF_FFFC.

View solution in original post

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