GPIOs in QORIQ processors

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GPIOs in QORIQ processors

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monalihaware
Contributor III

In a T-series processor,

1. Do Reset Control Word Status Registers(DCFG_CCSR_RCWSRn) reflect only RCW recieved from NOR flash or RCW received from any other source (including Hard coded RCW at POR)

2. Do GPIO programming require TLBs and MMU configuration?

3. Do GPIOs programming require PLLs to be correctly configured? 

3 Replies

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r8070z
NXP TechSupport
NXP TechSupport


Have a great day,

1 RCW data read from external memory is written to the RCW status registers.

2,3 GPIO programming require access to the CCSR address space. It means that QorIQ device has to complete reset sequence successfully i.e. the PLLs are locked. MMU configuration is required if core of the QorIQ device should programs GPIO configuration registers.

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248 Views
monalihaware
Contributor III

Thanks Serguei,

Thanks for your reponse. I consider that PLLs on my T2081 board are locked as it is coming out of POR sequence.

But why then PLL status register shows me "PLL disabled". Moreover i dont get any output at clk_out pin though i have programmed properly the clock configuration register for clk_out

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248 Views
r8070z
NXP TechSupport
NXP TechSupport

I meant platform PLL.  What PLL do you mean? 

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