In our custom hardware board (which is based on T1024-RDB), the PCIE endpoint device is connected in PCIE3 controller (SD_TX1_P) of T1024 SoC. The PCIE endpoint will generate an interrupt as an MSI message to PCIE3. The endpoint device is detected in the bus 1,device 0, function 0 in the T1024 SoC. The MSI is enabled for this domain/bus/function through the kernel routine (pcie_enable_msi ()).
The interrupt number of this PCIE endpoint is registered to the kernel using "request_irq ()" kernel routine. Still, the interrupt handler is not getting called, when the MSI interrupt is generated from the endpoint.
Even the interrupt count is not incremented in the /proc/interrupts in Linux.
But, the interrupt status is pending in the PCIe endpoint. We have confirmed this by dumping the PCIE configuration header (Command/Status Register). The MSI is enabled and the MSI address is configured in the endpoint device.
Please point out, whether any other changes is required in kernel source /device tree/ to enable MSI in PCIE3 controller.
We are using QorIQ SDK 2.0
Please perform the following tests:
1) In U-Boot write 0x50000000 to the 0xFE041740 (MPIC_MSIIRA) and read values of the MPIC_MSISRA (0xFE041720) and MPIC_MSIRA5 (0xFE041650).
2) In U-Boot write 0x50000000 to the 0xFE044140 (MPIC_MSIIRA alias) and read values of the MPIC_MSISRA (0xFE041720) and MPIC_MSIRA5 (0xFE041650).