Eval Board for 1000Base-KX LS1046A ?

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Eval Board for 1000Base-KX LS1046A ?

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matthej
Contributor II

Hi,

 

I have been looking for an eval board for the LS1046A device where I can test out my 1000Base-KX interface. I am planning on connecting the SerDes of the LS1046A directly to a Xilinx FPGA without any PHY.

 

Do you have an eval board that brings out any of the SerDes lines to a connector without a PHY involved? If not, do you have any idea on how I can test this?

 

Thanks,

 

Matty

 

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yipingwang
NXP TechSupport
NXP TechSupport

• All default SerDes settings are for 1G SGMII rather than 1000Base-KX. The following settings have been updated for 1000Base-KX, following the procedure in Lane Reset and Reconfiguration, prior to performing 1000Base-KX auto-negotiation:
• LNmGCR1 [REIDL_TH]
• LNmGCR1 [REIDL_EX_SEL]
• LNmGCR1 [REIDL_ET_MSB]
• LNmTECR0 [AMP_RED].

• After initializing the MAC and SERDES lane (s), and prior to initiating any 1000Base-KX traffic, perform the following 1000Base-KX protocol initialization:
o 1. Enable the 1000Base-KX AN reference clock by setting PLLnCR0 [DLYDIV_SEL] = 01, for the PLLn that is the clock source for the SGMII PCS (see TPLL_LES in General Control 0 - Lane a (LNaGCR0)).
o 2. Enable the 1000Base-KX AN module by setting PCCR8 [SGMIIp_KX] = 1, for each SGMII that will run in 1000Base-KX rather than SGMII mode.

Please apply these steps under U-Boot before loading Linux.

o 3. Initialize SGMII IF Mode register to 0x0008:
. SGMII_EN = 0
. USE_SGMII_AN = 0
. SGMII_SPEED = 10
o 4. Initialize 1000Base-KX (Clause 45) AN Millisecond Counter (simulation speedup only) to 0x0002
o 5. Initialize 1000Base-KX (Clause 45) AN Advertisement Register 1:TX_NONCE = unique value per device 

6. Read 1000Base-KX (Clause 45) AN Status Register to clear any previous status.

 

 

7. Initialize 1000Base-KX (Clause 45) AN Control Register to 0x1200:

. AN_ENAB = 1
. RST_AN = 1

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yipingwang
NXP TechSupport
NXP TechSupport

• All default SerDes settings are for 1G SGMII rather than 1000Base-KX. The following settings have been updated for 1000Base-KX, following the procedure in Lane Reset and Reconfiguration, prior to performing 1000Base-KX auto-negotiation:
• LNmGCR1 [REIDL_TH]
• LNmGCR1 [REIDL_EX_SEL]
• LNmGCR1 [REIDL_ET_MSB]
• LNmTECR0 [AMP_RED].

• After initializing the MAC and SERDES lane (s), and prior to initiating any 1000Base-KX traffic, perform the following 1000Base-KX protocol initialization:
o 1. Enable the 1000Base-KX AN reference clock by setting PLLnCR0 [DLYDIV_SEL] = 01, for the PLLn that is the clock source for the SGMII PCS (see TPLL_LES in General Control 0 - Lane a (LNaGCR0)).
o 2. Enable the 1000Base-KX AN module by setting PCCR8 [SGMIIp_KX] = 1, for each SGMII that will run in 1000Base-KX rather than SGMII mode.

Please apply these steps under U-Boot before loading Linux.

o 3. Initialize SGMII IF Mode register to 0x0008:
. SGMII_EN = 0
. USE_SGMII_AN = 0
. SGMII_SPEED = 10
o 4. Initialize 1000Base-KX (Clause 45) AN Millisecond Counter (simulation speedup only) to 0x0002
o 5. Initialize 1000Base-KX (Clause 45) AN Advertisement Register 1:TX_NONCE = unique value per device 

6. Read 1000Base-KX (Clause 45) AN Status Register to clear any previous status.

 

 

7. Initialize 1000Base-KX (Clause 45) AN Control Register to 0x1200:

. AN_ENAB = 1
. RST_AN = 1

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