Error while reading/writing NVSRAM via IFC

[draven]

Hello,

It is failed to read and write into NVSRAM, CY14V116N-BZ30XIT for NXP T1042, using following U-Boot revision;

U-Boot 2015.07 (Dec 19 2021 - 19:44:07 +0300)
powerpc-pokymllib32-linux-gcc (GCC) 5.2.0
GNU ld (GNU Binutils) 2.25.1

Following timing is set in uboot;

#define CONFIG_SYS_NVRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NVRAM_BASE) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_GPCM | \
CSPR_V)

#define CONFIG_SYS_NVRAM_AMASK IFC_AMASK(2*1024*1024)

#define CONFIG_SYS_NVRAM_BASE 0xc0000000
#define CONFIG_SYS_NVRAM_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NVRAM_BASE)

#define CONFIG_SYS_CSPR3_EXT 0xf
#define CONFIG_SYS_CSPR3 CONFIG_SYS_NVRAM_CSPR
#define CONFIG_SYS_AMASK3 CONFIG_SYS_NVRAM_AMASK
#define CONFIG_SYS_CSOR3 CSOR_NOR_TRHZ_20
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0xff) | \
FTIM0_GPCM_TEADC(0xff) | \
FTIM0_GPCM_TEAHC(0xff))
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0xff))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xff) | \
FTIM2_GPCM_TCH(0xff) | \
FTIM2_GPCM_TWP(0xff))
#define CONFIG_SYS_CS3_FTIM3 0x0

In uboot terminal, md is called to observe the content of SRAM

=> md 0xfc0000000
c0000000: 00000000 00000000 00000000 00000000 ................

Then mw is used to write some data into SRAM.

If it is called twice and it has word size of data, it works;

=>
=> mw.w fc0000000 1234
=> mw.w fc0000000 1234
=> md fc0000000 4
c0000000: 12340000 00000000 00000000 00000000 .4..............
=>

If it is written once it returns wild data at the first md command;

=> mw.w fc0000000 5678
=> md fc0000000 4
c0000000: c000c000 c000c000 c000c000 c000c000 ................
=> md fc0000000 4
c0000000: 56780000 00000000 00000000 00000000 Vx..............
=>

If a repetitive alphanumeric hexa number like baba, cece, dede, it can't be written;

=> mw.w fc0000000 baba
=> mw.w fc0000000 baba
=> md fc0000000 4
c0000000: 00000000 00000000 00000000 00000000 ................

If repetitive numbers are numeric, it can be written into SRAM;

=> mw.w fc0000000 1212
=> mw.w fc0000000 1212
=> md fc0000000 4
c0000000: 12120000 00000000 00000000 00000000 ................

Can you please help us by commenting on this problem?

Best regards

[draven]

hi @yipingwang ,

thanks for your reply,

According to your reply I tried to find gpcm timing ; 

1. FTIM0
   • TACSE = tSA (nvsram parameter) (Address setup to start of write) : 0 = 1
   • TEADC : 4 (this parameter is about latch so I added the value which working at nor-flash)
   • TEAHC : 3 (this parameter is about latch so I added the value which working at nor-flash)

       2. FTIM1

• TACO = tLZOE (nvsram parameter) : 3 =  3/13 = 1
•  TRAD = I added your value

     3. FTIM2

• TCS = tSA (nvsram parameter) (Address setup to start of write) : 0 = 1
• TCH = tHA (nvsram parameter) (Address hold after end of write) : 0 = 1
• TWP = tPWE (nvsram parameter) (Write pulse width) : 24 = 24/13 = 2

   4. FTIM3

TAAD = tAA (nvsram parameter) (Address access time) : 30 = 30/13 = 2

And our gpcm parameter like this :

#define CONFIG_SYS_NVRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NVRAM_BASE) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_GPCM | \
CSPR_V)

#define CONFIG_SYS_NVRAM_AMASK IFC_AMASK(2*1024*1024)

#define CONFIG_SYS_CSPR3_EXT 0xf
#define CONFIG_SYS_CSPR3 CONFIG_SYS_NVRAM_CSPR
#define CONFIG_SYS_AMASK3 CONFIG_SYS_NVRAM_AMASK
#define CONFIG_SYS_CSOR3 0
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x1) | \
FTIM0_GPCM_TEADC(0x4) | \
FTIM0_GPCM_TEAHC(0x3))
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x1) | \
FTIM1_GPCM_TRAD(12))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(1) | \
FTIM2_GPCM_TCH(1) | \
FTIM2_GPCM_TWP(2))
#define CONFIG_SYS_CS3_FTIM3 0x2

But I got same result as before. Do you have any comment? Are my parameters and calculations correct?

[yipingwang]

The FTIM Timing Registers (FTIM0-FTIM3) must be programmed per the values specified in the SRAM datasheet mapped to IFC module.

According to T1042 RM, ip_clk is IFC module input clock, divided clock from platform clock. ip_clk = 1/2 * (Platform Clock).

IFC_CLK is used when IFC was selected as GPCM mode. IFC_CLK was divided clock from ip_clk. IFC_CLK = 1/(CCR[CLK_DIV] + 1) * ip_clk. IFC_CLK cycle is 1/IFC_CLK.

Take GPCM_FTIM1[TRAD] for example, T1042 platform clock is 600 MHz, then IFC ip_clk = 300 MHZ, and CCR[CLK_DIV] = 3 (IFC:CCR = 0x03008000), then IFC_CLK = 75 MHZ. (IFC_CLK cycle tIFC = 1/75MHz = 13.3 ns).

According to T1042RM GPCM read operation, for non-burst mode TRAD value should be programmed as {(2 + n)*(CCR[CLK_DIV] + 1)}, where n defines the memory access time in terms of IFC_CLK. Memory takes n ifc_clk to output data after output enable is asserted or after new address is sampled. n can take values 0,1,2,3...

According to CY14V116N-BZ30XIT has (OE# Output enable to data valid) tDOE <= 14 ns So we can conclude that TRAD should be <= (floor(14ns/13.3) + 2) * (3 + 1) = (1 + 2) * 4 = 12.

1. Suggest customer set FTIM Timing Registers (FTIM0-FTIM3) with correct value according to T1042/SRAM datasheet.
2. Mesure IFC read/write waveform to met CY14V116N-BZ30XIT timing specification.