We have been trying to test ECC single bit error correction with limited success. The test carried out was similar to the one described in AN3538 for error detection but the test result did not meet our expectation. It reports SSBEC errors but the content of memory remains unchanged. The only explanation I can come up with to explain the behavior: is that the algorithm some how decided the bit to be fixed was in ECC memory which remains hidden from our view. Is this a plausible explanation?
Can you provide a test that would expose an ECC correction in ddr memory?
Second question: The ls1021a reference manual rev 3 refers to ECC_SCRUB_EN once but it is never defined in any register. Which register is ECC_SCRUB_EN defined in? or are we forced to use periodic scrubbing? The hope would be to use ECC_SCRUB_EN to use read operation to scrub (or correct) the memory being read.
Thank you in advance for your support
> the algorithm some how decided the bit to be fixed was in ECC memory which remains hidden from our view.
DDR memory controller detects and corrects all single-bit errors within the data bus - refer to the QorIQ LS1021A Reference Manual, 16.5.7 Error Checking and Correcting (ECC).
> Can you provide a test that would expose an ECC correction in ddr memory?
Not shure what do you mean (see answer above), but you could set DDR_SDRAM_CFG[ECC_EN]=0 to see DDR SDRAM errors.
> The ls1021a reference manual rev 3 refers to ECC_SCRUB_EN
The bit in question is DDR_SDRAM_CFG_3[ECC_FIX_EN].