ECC interrupts on LS1046

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ECC interrupts on LS1046

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hecheng
Contributor I

Hi all,

I'm working on LS1046 ARM board and want to use ECC. In LS1046A Reference Manual, it mentions that "when an enabled interrupt condition occurs, the internal int_B signal is asserted to the programmable interrupt controller (PIC)". However, this is really confusing.

  • What kind of interrupt is int_B signal? How to handle it?
  • Is PIC provided on LS1046 board? I cannot find enough info about PIC in LS1046A Reference Manual.

In our project, GIC is used to manage interrupts. So I'm wondering if the info is already outdated and if ECC interrupts should be managed by GIC instead of PIC. If so, what interrupt ID is assigned to ECC interrupt?

Thanks in advance.

Regards,

He

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2 Replies

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r8070z
NXP TechSupport
NXP TechSupport


Have a great day,

I can see “the internal int_B signal is asserted to the programmable interrupt controller (PIC)" in the T1040 reference manual. The T10xx devices have the multicore Programmable Interrupt Controller. So that was just inherited and should be corrected for the LS1046 where is GIC instead of PIC. According to Table 5-1. Interrupt assignments of the LS1046 reference manual ECC interrupt (DDR controller error) Internal Interrupt Number is 176.

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hecheng
Contributor I

Hi Serguei,

Thanks for your reply.

I have another few questions:

1. Now I am able to inject a double-bit error in noncached SDRAM and it triggers a synchronous interrupt. Do you why is it synchronous interrupt instead of System Error?

2. If a single-bit error happens in L1/L2 cache, would single-bit error counter ERR_SBE[SBEC] increment? Or ERR_SBE[SBEC] only increments if a single-bit error occurs in DRAM?

3. I also found a wierd thing that even if ERR_INT_EN[MBEE] is disabled, double-bit error can still trigger an interrupt (ERR_DISABLE[MBED] is 0 and DDR_SDRAM_CFG[ECC_EN] is 1). Do I miss some configuration? Or this register is not needed for enabling ECC interrupts?

4. If I want to handle the ECC interrupt via GIC, what is the configuration that should be done?

5. How to configure ECC on OCRAM and L1/L2 cache? And how to inject ECC errors in OCRAM and Cache?

Best,

He

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