DDR3 ECC crashes on LS1021A IOT customized design

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DDR3 ECC crashes on LS1021A IOT customized design

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Contributor III

Hello,

We have designed a board base on the ls1021aiot (SPF28203B.pdf Oct 2015). Our board uses the LS1020a (LS1020AXE7HNB) instead of the ls1021a and uses a memory reduced in size (MT41K256M16HA-107). We have been working with it for the last year without any problem on the DDR3 memory side. It is my understanding that the LS1020 supports ECC and the IOT support ECC by using a third DRR3 chip.

Lately, we have been trying to get ECC to work without success. The system crashes in u-boot get_ram_size() as soon as DDR is accessed. The D_INIT value remains at 1, indicating the initialisation did not complete properly. When error checking is enabled with ECC enabled, the system reports an ACE (Automatic calibration error) which can be seen in the log (failedCalibrationlog2.txt).

The software modifications were inspired by AN3538. Logs are attached to demonstrate register current (and previous content) at key places in the initialisation process. 2 logs were provided: 1- without ECC (successfulCalibrationLog2.txt) , 2- with ECC enabled (failedCalibrationlog2.txt).  Also attached are the RCW and DDR controller registers content for our working software (no ECC).

Hardware wise, the schematics for our design and for the IOT are the same the third ddr3 chip. 

It is not clear what calibration does and what I can do to find the related problem?

Are there other items, I could check in relation to the described problem?

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NXP TechSupport
NXP TechSupport

I would notice two points:

1. As per your logs, DDR data rate is set to 2000MT/s. This is too much, the maximum supported by the LS1021A SDRAM data rate of 1600MT/s.

2. The LS1021A supports four ECC bits only, this requires following setting:  DDR_SDRAM_CFG[ACC_ECC_EN]=1.

Regards,

Bulat

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NXP TechSupport
NXP TechSupport

I would notice two points:

1. As per your logs, DDR data rate is set to 2000MT/s. This is too much, the maximum supported by the LS1021A SDRAM data rate of 1600MT/s.

2. The LS1021A supports four ECC bits only, this requires following setting:  DDR_SDRAM_CFG[ACC_ECC_EN]=1.

Regards,

Bulat

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Contributor III

Thank you for you last reply, it helped successfully test error detection using AN3538.

In a similar way, I was trying to test single error correction by reading a memory area.

And found the following in the reference manual. The DDR controller also supports ECC scrubbing, which is enabled via
DDR_SDRAM_CFG_3[ECC_SCRUB_EN]. In this mode, all single-bit errors detected
will be fixed by hardware. 

However, ECC_SCRUB_EN cannot be found anywhere else in the ls1021 reference manual rev 3 or in the DDR_SDRAM_CFG_3 register bits

 

Why is ECC_SCRUB_EN not available in the sdram config3 as mentionned?

For some reason, the DDR memory works with the 2000MT/s setting?

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