Hello,
I am using P1020RM in my current design.
In design, there are Two DDR-3 memory connected with P1020RM.
In earlier design, it was working fine @200MHz clock frequency and below are the hardware setting for 200MHz clock,
Now we want to increase the clock frequency to 333MHz and for that we made changes from code warrior QCVS for register setting and apply in our u-boot code but It's not working.
Below are the hardware setting for 333MHz clock,
Observation:-
With some different register setting,
With some other different register setting,
Can any one provide the correct register and hardware setting to work DDR-3 @333MHz clock frequency?
DDR3 Part# AS4C512M8D3A-12BIN
Regards,
Alpesh.
It looks like you use 16-bit DDR3 bus width. Our developemnt boards have 32-bit memory bus, below is the memory dump of the DDR3 controller working at 333MHZ MCK frequency:
ffe02000: 0000003f 00000000 00000000 00000000
ffe02010: 00000000 00000000 00000000 00000000
ffe02080: 80014302 00000000 00000000 00000000
ffe02090: 00000000 00000000 00000000 00000000
ffe020a0: 00000000 00000000 00000000 00000000
ffe020b0: 00000000 00000000 00000000 00000000
ffe020c0: 00000000 00000000 00000000 00000000
ffe020d0: 00000000 00000000 00000000 00000000
ffe020e0: 00000000 00000000 00000000 00000000
ffe02020: 00000000 00000000 00000000 00000000
ffe02030: 00000000 00000000 00000000 00000000
ffe02040: 00000000 00000000 00000000 00000000
ffe02050: 00000000 00000000 00000000 00000000
ffe02060: 00000000 00000000 00000000 00000000
ffe02070: 00000000 00000000 00000000 00000000
ffe020f0: 00000000 00000000 00000000 00000000
ffe02100: 00020000 00110104 5d59e544 0fa888cd
ffe02110: c70c0008 24401000 00441210 00000000
ffe02120: 00000000 0a280100 deadbeef 00000000
ffe02130: 03000000 00000000 00000000 00000000
ffe02140: 00000000 00000000 00000000 00000000
ffe02150: 00000000 00000000 00000000 00000000
ffe02160: 00000001 01401400 00000000 00000000
ffe02170: 89080600 8675f608 00000000 00000000
ffe02180: 00000000 00000000 00000000 00000000
ffe02190: 00000000 00000000 00000000 00000000
ffe021a0: 00000000 00000000 00000000 00000000
ffe021b0: 00000000 00000000 00000000 00000000
ffe021c0: 00000000 00000000 00000000 00000000
ffe021d0: 00000000 00000000 00000000 00000000
ffe021e0: 00000000 00000000 00000000 00000000
ffe021f0: 00000000 00000000 00000000 00000000
Regards,
Bulat
Hello Bulat,
Thank you very much for your response.
We used your value but unfortunately that did not work for me.
We have modified some registers' value from your value which work for me.
Below is the table showing all registers' value which we used for 333MHz clock frequency.
Offset address (hex) | Register name | Value for 333MHz |
---|---|---|
2000 | DDR_CS0_BNDS | 0x0000003F |
2008 | DDR_CS1_BNDS | 0x00000000 |
2080 | DDR_CS0_CONFIG | 0x80014402 |
2084 | DDR_CS1_CONFIG | 0x00000000 |
20C0 | DDR_CS0_CONFIG_2 | 0x00000000 |
20C4 | DDR_CS1_CONFIG_2 | 0x00000000 |
2100 | DDR_TIMING_CFG_3 | 0x00050000 |
2104 | DDR_TIMING_CFG_0 | 0x00110104 |
2108 | DDR_TIMING_CFG_1 | 0x5D592544 |
210C | DDR_TIMING_CFG_2 | 0x0FA890CD |
2110 | DDR_DDR_SDRAM_CFG | 0xC7140008 |
2114 | DDR_DDR_SDRAM_CFG_2 | 0x24401010 |
2118 | DDR_DDR_SDRAM_MODE | 0x00441210 |
211C | DDR_DDR_SDRAM_MODE_2 | 0x00000000 |
2120 | DDR_DDR_SDRAM_MD_CNTL | 0x00000000 |
2124 | DDR_DDR_SDRAM_INTERVAL | 0x0A280100 |
2128 | DDR_DDR_DATA_INIT | 0xDEADBEEF |
2130 | DDR_DDR_SDRAM_CLK_CNTL | 0x03000000 |
2148 | DDR_DDR_INIT_ADDR | 0x00000000 |
214C | DDR_DDR_INIT_EXT_ADDR | 0x00000000 |
2160 | DDR_TIMING_CFG_4 | 0x00000001 |
2164 | DDR_TIMING_CFG_5 | 0x01401400 |
2170 | DDR_DDR_ZQ_CNTL | 0x89080600 |
2174 | DDR_DDR_WRLVL_CNTL | 0x8675F608 |
217C | DDR_DDR_SR_CNTR | 0x00000000 |
2180 | DDR_DDR_SDRAM_RCW_1 | 0x00000000 |
2184 | DDR_DDR_SDRAM_RCW_2 | 0x00000000 |
Thanks again.
Regards,
Alpesh.
Of course values needed to be modified in accordance with your bus width and specific DDR3 device parameters. Am I correct that DDR3 memory is now working?
Regards,
Bulat
Hello Bulat,
Yes, You're right.
The DDR-3 memory is now working with this new settings.
Thanks again.
Regards,
Alpesh.