We have made a board with a T4240. On the board, we installed a DDR3_ SODIMM slot, and we used one 4GB DDR3L-1600 CL9 204-Pin SODIMM ( see figure 2 ). But when we do DDR initialization, the serial communication interface shows a message"2 GB left unmapped"(See figure 1). Why?
Figure 1
Figure2
ok, AS the below shows.
U-Boot 2015.01+SDKv1.9+geb3d4fc (Aug 01 2016 - 20:19:47)
CPU0: T4240E, Version: 2.0, (0x82480020)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1800 MHz, CPU1:1800 MHz, CPU2:1800 MHz, CPU3:1800 MHz,
CPU4:1800 MHz, CPU5:1800 MHz, CPU6:1800 MHz, CPU7:1800 MHz,
CPU8:1800 MHz, CPU9:1800 MHz, CPU10:1800 MHz, CPU11:1800 MHz,
CCB:733.333 MHz,
DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), IFC:183.333 MHz
FMAN1: 733.333 MHz
FMAN2: 733.333 MHz
QMAN: 366.667 MHz
PME: 533.333 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 1605001b 18101b16 00000000 00000000
00000010: 6c6e0848 00448c00 0c020000 f5000000
00000020: 00000000 ee0000ee 00000000 000287fc
00000030: 00000000 50000000 00000000 00000028
Board: T4240RDB, Board rev: 0xff CPLD ver: 0xffff, vBank: 7
SERDES Reference Clocks:
SERDES1=100MHz SERDES2=156.25MHz
SERDES3=100MHz SERDES4=100MHz
I2C: ready
SPI: ready
DRAM: Initializing....using SPD
Detected UDIMM KHX1600C9S3L/4G
There is no rank on CS0 for controller 1.
There is no rank on CS0 for controller 2.
Not all controllers have compatible interleaving mode. All disabled.
Waiting for D_INIT timeout. Memory may not work.
2 GiB left unmapped