My custom design has a serious DDR problem, I have 16 GB total amount of Physical ram on design. Corresponding U-boot log (taken with Code Warrior -> Connect -> Debug session).
I changed recommended U-boot parameteres for my design in it's source code ( Ram size = 4*4096, CPU_FREQ=100MHZ and DDR_FREQ = 100MHZ)
I attached RCW configurations taken from QCVS.
Is there any way to close SPD check to skip this step ?
Or is there any way to fix this issue ?
1-) I also made a DDR test using Hardware Diagnostic Tool of Code Warrior PA. Settings are attached. I just tested first 2 Mbyte of DDR and test passed.
2-) When I remove physical ram of T1042D4 Reference Demo board from it's slot, U-boot is exactly giving the same error.
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word(RCW):
00000000: 080a000a 0a000000 00000000 00000000
00000010: 06000002 00408102 fc027000 21002000
00000020: 00800000 00000000 60000000 0003a001
00000030: 00000100 c0165005 00000000 00000000
Board rev: 0x01 CPLD ver: 0x05, vBank: 0x7
DRAM: Initializing....using SPD
DDR: failed to read SPD from address 81
Error: No valid SPD detected.
*** failed ***
initcall sequence effcf3f8 failed at call eff5ce5c (err=1)
### ERROR ### Please RESET the board ###
Memory test is not working. It was working when I use CPC as SRAM and memory map it at offset 0. When I try to use init_core.tcl instead of init_sram.tcl ( which initialized DDR registers ). Memory test fails at first step ( Walking ones test )