DDR Address Decoding!

[qammarabbas]

Hi,

I am trying to figure out the address decoding of a 8Gbit micron DDR3 RAM(with 8 logical banks) device.The datasheet mentions that 16 bits are used for row address and 10 bits are used for column address. According to the given information, the size of a single bank  will be 2^16 (rows) * 2^7 (columns). Why is there another x128 mentioned in the block diagram? 
Please find the attached image for your information. Thank you!

[r8070z · Accepted solution]

Have a great day,

I see form attached picture that datasheet should say that there are 16-bit row address, 10-bit column address, 3-bit bank address and dataword width is 16-bit. Hence single bank capacity is (rows*columns*width) = 2^16*2^10*16 bits = 1 Gb.

DDR3 SDRAM's prefetch buffer size is 8n (eight datawords per memory access), i.e. for 16-bit datword prefetch buffer size is 8*16=128 bits. From 10-bit column address of 16-bit dataword the 7 msb select 128-bit chunk for prefetch on memory access. The rest 3 lsb select dataword in the prefetched 128-bit.

So on the figure they prefer present 2^16*2^10*16 bits in a single bank as 2^16*(2^7*10^3)*(2^4) bits = 65536*128*128 bits

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[qammarabbas]

Thanks a lot!