Configuring CPC as I/O stash on t1040

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Configuring CPC as I/O stash on t1040

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samuelstearley
Contributor I

I would like to ensure that data received over PCIe or Ethernet is available in L3 for quick processing.

Are there any examples or documentation explaining how to configure a portion of the CPC as I/O stash on a t1040?

I imagine that I'll have to 1) create a partition, 2) setup the partition ID register to match the I/O traffic, 3) assign a couple of the L3 ways to this new partition.

What do the bits in the CPC partition ID register represent?  On a different SOC, the p4080, they are a bit array of CSD_IDs, however the t1040 does not have any CSD_IDs in the LAWs.

The simple lazy implementation: ?

As a starting point, is it enough that I set the "DSTALLOC" bit in the default partition register "CPC_CPCPAR0" ? Then all possible writes from anywhere (to ddr) will allocate in L3 ?  Including writes from I/O ?  This would be a first cut implementation as it won't dedicate any of the cache ways to the I/O traffic.

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yipingwang
NXP TechSupport
NXP TechSupport

Hello Samuel Stearley,

For explicit CPC stashing, the PAACT tables used by PAMU for transaction authorization and translation must be correctly programmed. The CPC implicit (address range based) stash allocation ranges are defined by "Stashing Control Registers". PCIe will only stash if the CPC has been set up to stash on the address range that the PCI transaction translates to. 


Have a great day,
TIC

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