Hi, I’m interested in using instructions for data cache locking. From the manual I saw there are instructions like dcbtls or dcblc for locking or unlocking cache lines. My idea is: suppose a core wants to use the variable y, before using y the core finds the address of y and it uses the instruction dcbtls for locking the cache line specified by the address found before.
I have another question: how these instructions impact the allocation of data in the shared cache?
