CPU system version register (SVR) mismatch

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CPU system version register (SVR) mismatch

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christiansielaf
Contributor III

Hi all,

on our new Controller module where we use the QorIQ LS1 device we had a strange behavior!

After Power ON the BL starts normally and shows CPU revision LS1021A (DCFG_CCSR_SVR register is 0x87081120). But after booting our OS and then rebooting from OS/Linux the bootloader seems to be running on different CPU???... The BL shows that CPU is LS1020 and DCFG_CCSR_SVR register read is 0x87081020. We also stopped in BL CLI after reboot and manually read the register as a memory – it shows different value!

All that is OK according to documentation, but why on Earth the hard-coded CPU revision and personality is changing? Could that be, that the POR processor IO state is wrong and this is causing this weird behavior? Or simply a new silicon bug?

We realy appreciate your response.

Best regards and thank you in advance,

Christian

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christiansielaf
Contributor III

Hello Ufedor,

thank you very much for your help and the rapid answer ... ;-)!

Best regards and thank you in advance

Christian S.

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ufedor
NXP Employee
NXP Employee

Please note that IFC_A16 must be pulled down and IFC_A17 must be pulled up during power-on reset for the LS1021A.

It is required to check levels on these signals during POR.

If further issue investigation will be needed please consider to create a technical case:

https://community.freescale.com/thread/381898

and provide the processor connection schematics for inspection.

531 Views
christiansielaf
Contributor III

Hello Ufedor,

thank you very much for your help and the rapid answer!

The IFC_A16 Pin has an pull down but there isn't a pull up at IFC_A17! Where I can find in the documents this requirement?

Best regards and thank you in advance

Christian S.

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531 Views
ufedor
NXP Employee
NXP Employee

AN4878, QorIQ LS1021A Design Checklist - Application Note  (REV 1):

http://cache.nxp.com/files/32bit/doc/app_note/AN4878.pdf

page 24