B4860 DDR init issue

[qiaofa_luo]

Hello NXP freescale team;
    We are debuging b4860 u-boot(sdk-1.6) , we encount ddr init issue, we use 6GB ddr size,

4 GB for ddr10 controller, 2 ranks

2 GB for ddr1 controller, 1 ranks,

and the error log information as follows:

DDR: failed to read SPD from address 81
SPD error on controller 0! Trying fallback to raw timing calculation
Detected UDIMM RAW timing DDR
There is no rank on CS0 for controller 1.
Not enough bank(chip-select) for CS0+CS1 on controller 1, interleaving disabled!
Waiting for D_INIT timeout. Memory may not work.
2 GiB left unmapped

[sonminh]

Hi all,

Have you been resolve this problem. I had the trouble the same as you with coustom board use b4860

Thanks and brgs

[qiaofa_luo]

thank very much YiPIng:

I understand the spd now, but the n_ranks is board specific, and we can't get the SPD data from the micron offical now,

may be is old?

our board use MT41K256M16TW-107IT,  and it is as the B4860QDS board MT41K256M16HA-107,

they are very identical, but we don't have the B4860QDS board

could help us to dump the spd bin from b4860qds borad(in uboot) for reference. 

than you very much

[yipingwang]

spd_1866_dual_rank_4GB_DDRC1.bin:

=> i2c read 0x51 0 0x80 0x1000000
=> md 0x1000000 0x80
01000000: 81100b02 0419000a 0b110108 0900e002    ................
01000010: 70787030 70111088 20083c3c 0118830d    pxp0p... .<<....
01000020: 0000caa6 a6a6a600 00000000 00000000    ................
01000030: 00000000 00000000 00000000 0f110401    ................
01000040: 00000000 00000000 00000000 00000000    ................
01000050: 00000000 00000000 00000000 00000000    ................
01000060: 00000000 00000000 00000000 00000000    ................
01000070: 00000000 0002fe4a 09162b08 165ee614    .......J..+..^..
01000080: deadbeef deadbeef deadbeef deadbeef    ................
01000090: deadbeef deadbeef deadbeef deadbeef    ................
010000a0: deadbeef deadbeef deadbeef deadbeef    ................
010000b0: deadbeef deadbeef deadbeef deadbeef    ................
010000c0: deadbeef deadbeef deadbeef deadbeef    ................
010000d0: deadbeef deadbeef deadbeef deadbeef    ................
010000e0: deadbeef deadbeef deadbeef deadbeef    ................

spd_1866_single_rank.bin:

=> i2c read 0x53 0 0x80 0x2000000
=> md 0x2000000 0x80
02000000: 81100b02 04190002 0b110108 0900e002    ................
02000010: 70787030 70111088 20083c3c 0118830d    pxp0p... .<<....
02000020: 0000caa6 a6a6a600 00000000 00000000    ................
02000030: 00000000 00000000 00000000 0f110401    ................
02000040: 00000000 00000000 00000000 00000000    ................
02000050: 00000000 00000000 00000000 00000000    ................
02000060: 00000000 00000000 00000000 00000000    ................
02000070: 00000000 0002fe4a 09162b08 165e3d38    .......J..+..^=8
02000080: deadbeef deadbeef deadbeef deadbeef    ................
02000090: deadbeef deadbeef deadbeef deadbeef    ................
020000a0: deadbeef deadbeef deadbeef deadbeef    ................
020000b0: deadbeef deadbeef deadbeef deadbeef    ................
020000c0: deadbeef deadbeef deadbeef deadbeef    ................
020000d0: deadbeef deadbeef deadbeef deadbeef    ................
020000e0: deadbeef deadbeef deadbeef deadbeef    ................

[qiaofa_luo]

thank you very much, YiPing.

[qiaofa_luo]

Hi YiPing:
Could you give us a copy of SPD bin file 

spd_1866_dual_rank_4GB_DDRC1.bin and 

spd_1866_single_rank.bin for reference?

thank you very much

[yipingwang]

The SPD binary should be provided by the DDR manufacturer for different type DDR.

Thanks,

Yiping

[yipingwang]

Hello Luo Bob,

On B4860QDS, SPD for  DDRC1 is at address 0x51, SPD for DDRC2 is at address 0x53, if they are different from your custom board, please modify the following section in include/configs/B4860QDS.h in u-boot source code. In addition, only 2G DDR is mapped in u-boot memory map.

#define CONFIG_SYS_SPD_BUS_NUM  0
#define SPD_EEPROM_ADDRESS1     0x51
#define SPD_EEPROM_ADDRESS2     0x53

#define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SDRAM_SIZE   2048    /*

Please refer to the following command to write SPD binary to i2c EEPROM.

mw.b 0xffdf0055 0x8
tftp 1000000 spd_1866_dual_rank_4GB_DDRC1.bin
i2c write 0x1000000 0x51 0 0x80
reset
tftp 2000000 spd_1866_single_rank.bin
i2c write 0x2000000 0x53 0 0x80
reset

If there is no valid SPD on your target board, you could use raw timing to calculate DDR controller configuration parameters to initialize the custom board. 

Please refer to the following data structures defined in board/freescale/b4860qds/ddr.c in u-boot, you need to create a QCVS DDR project, modify the DDR properties panel according to your DDR datasheet and create the generic DDR configuration parameters set, then use DDRv tool to connect to the target board to do validation and optimization to get the final optimized parameters and use them to modify the following parts in u-boot.

dimm_params_t ddr_raw_timing = {
        .n_ranks = 2,
        .rank_density = 2147483648u,
        .capacity = 4294967296u,
        .primary_sdram_width = 64,
        .ec_sdram_width = 8,
        .registered_dimm = 0,
        .mirrored_dimm = 1,
        .n_row_addr = 15,
        .n_col_addr = 10,
        .n_banks_per_sdram_device = 8,
        .edc_config = 2,        /* ECC */
        .burst_lengths_bitmask = 0x0c,

        .tckmin_x_ps = 1071,
        .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
        .taa_ps = 13910,
        .twr_ps = 15000,
        .trcd_ps = 13910,
        .trrd_ps = 6000,
        .trp_ps = 13910,
        .tras_ps = 34000,
        .trc_ps = 48910,
        .trfc_ps = 260000,
        .twtr_ps = 7500,
        .trtp_ps = 7500,
        .refresh_rate_ps = 7800000,
        .tfaw_ps = 35000,
};

static const struct board_specific_parameters udimm0[] = {
        /*
         * memory controller 0
         *   num|  hi|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
         * ranks| mhz|adjst| start |   ctl2    |  ctl3  |      |delay |
         */
        {2,  1350,    4,     7, 0x09080807, 0x07060607,   0xff,    2,  0},
        {2,  1666,    4,     7, 0x09080806, 0x06050607,   0xff,    2,  0},
        {2,  1900,    3,     7, 0x08070706, 0x06040507,   0xff,    2,  0},
        {1,  1350,    4,     7, 0x09080807, 0x07060607,   0xff,    2,  0},
        {1,  1700,    4,     7, 0x09080806, 0x06050607,   0xff,    2,  0},
        {1,  1900,    3,     7, 0x08070706, 0x06040507,   0xff,    2,  0},
        {}
};

Thanks,

Yiping