I have no LS1043ARDB boards here. The newer one is SCH-28529 REV C1 and the older one is SCH-28529 REV C. The differences log on the schematic for REV C1 says the only difference is setting the EVDD in the CPLD, however I am noticing strange behaviour. I've made some software changes (still trying to narrow down which) and the REV C board hangs at startup when I initialize all 4 CPUs. The only way I can get it work is to just initialize one. The REC C1 board is fine in both cases.
There are other issue with the Rev C. I have run from bank v4 because bank v0 can't run 'dhcp' successfully, and I think something is wrong with the NAND because u-boot prints out this:
Using SERDES1 Protocol: 5205 (0x1455)
Flash: 128 MiB
NAND: fsl_ifc_read_byte beyond end of buffer
fsl_ifc_read_byte beyond end of buffer
fsl_ifc_read_byte beyond end of buffer
fsl_ifc_read_byte beyond end of buffer
Is there anything not listed between the Rev C and C1 that explains this CPU problem?
It is reasonable to investigate the issue as a Technical Case: